
MB90220 Series
44
(2) Block Diagram
Control signals
Dedicated baud rate generator
External clock
Clock selector
Receiving clock
Transmitting clock
Receiving interrupt
(to CPU)
SCK3
Transmission interrupt
(to CPU)
Transmission controller
Transmission
start circuit
Transmitted
bit counter
Transmission
parity counter
SOD3
Transmitting shifter
SODR
Start of
transmission
Receiving controller
Start bit detector
Received
bit counter
Received
parity counter
Receiving shifter
End of
reception
SIDR
Received status
determination circuit
Signal indicating occurrence
of receiving error for EI
2
OS (to CPU)
F
2
MC-16 bus
SMR
register
SCR
register
MD1
MD0
CS2
CS1
CS0
BCH
SCKE
SOE
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
Control signals
SID3
16-bit reload timer 4
(internally connected)