參數(shù)資料
型號(hào)： MB90P224A
廠商： Fujitsu Limited
英文描述： 8-Bit Proprietary Microcontroller(8位專用微控制器)
中文描述： 8位微控制器專利（8位專用微控制器）
文件頁數(shù)： 47/105頁
文件大?。?/td> 1130K
代理商： MB90P224A
47
MB90220 Series
7. DTP/External Interrupts
DTP (Data Transfer Peripheral) is located between external peripherals and the F
2
MC-16F CPU. It receives a
DMA request or an interrupt request generated by the external peripherals and reports it to the F
2
MC-16F CPU
to activate the extended intelligent I/O service or interrupt handler. The user can select two request levels of “H”
and “L” for extended intelligent I/O service or, and four request levels of “H,” “L,” rising edge and falling edge for
external interrupt requests. In MB90220, only parts corresponding to INT2 to INT0 are usable as external
interrupt/DTP request.
Parts corresponding to INT7 to INT3 cannot be used as external interrupt/DTP request, but only for edge
detection at external terminals.
Note: INT7 to INT3 are not usable as DTP/external interrupts.
(1) Register Configuration
(2) Block Diagram
bit15
ER7
bit14
ER6
bit13
ER5
bit12
ER4
bit11
ER3
bit10
ER2
bit9
ER1
ER0
bit8
00003A
H
bit7
EN7
bit6
EN6
bit5
EN5
bit4
EN4
bit3
EN3
bit2
EN2
bit1
EN1
EN0
bit0
00003B
H
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
00003D
H
00003C
H
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
ENIR
00000000
B
00000000
B
EIRR
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
00000000
B
ELVR
ELVR
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
00000000
B
Register name Address
Register name Address
Register name Address
Register name Address
Initial value
Initial value
Initial value
Initial value
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
DTP/Interrupt Enable Register (ENIR)
Request Level Setting Register (ELVR)
DTP/Interrupt Source Register (EIRR)
Interrupt/DTP enable register
4
Gate
4
Source F/F
Edge detector
8
Interrupt/DTP source register
4
Request level setting register
8
Request input
F
2
M
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