![](http://datasheet.mmic.net.cn/330000/MB90P224BPF_datasheet_16438137/MB90P224BPF_34.png)
MB90220 Series
34
(Continued)
: EI
2
OS is supported (with stop request).
: EI
2
OS is supported (without stop request).
: EI
2
OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI
2
OS is used
for one of the two, EI
2
OS and ordinary interrupt are not both available for the other (with stop request).
: EI
2
OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI
2
OS is used
for one of the two, EI
2
OS and ordinary interrupt are not both available for the other (without stop request).
: EI
2
OS is not supported.
Note: Since the interrupt sources having interrupt vector Nos. 15 to 18, 20, and 25 to 28 are OR’ed, respectively,
select them by means of the interrupt enable bits of each resource.
If EI
2
OS is used with the above-mentioned interrupt sources OR’ed with the interrupt vector Nos. 15 to 18,
20, and 25 to 28, be sure to activate one of the interrupt sources.
Also in this case, a request flag in the same series as the one interrupt source is likely to be cleared
automatically by EI
2
OS.
Assume for example that an interrupt for compare 4 of the interrupt vector No. 25 is activated at this time by
ICR07, so that the compare 6 is disabled. If EI
2
OS is activated at this time by ICR07, so that the compare 6
interrupt takes place during generation of or simultaneously with the compare 4 interrupt, not only the interrupt
flag for the compare 4 but also that for the compare 6 will be automatically cleared after EI
2
OS is automatically
transferred due to the compare 4 interrupt.
Interrupt source
EI
2
OS
support
Interrupt vector
Interrupt control
register
No.
Address
ICR
Address
UART0 (ch.0) reception completed
#39
27
H
FFFF60
H
ICR14
0000BE
H
Delay interrupt generation module
×
×
#42
2A
H
FFFF54
H
ICR15
0000BF
H
Stack fault
#255
FF
H
FFFC00
H
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