參數(shù)資料
型號: MB91110PMT2
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP144
封裝: PLASTIC, LQFP-144
文件頁數(shù): 48/98頁
文件大?。?/td> 1049K
代理商: MB91110PMT2
MB91110 Series
52
13. Interruption Control Register (ICR)
This function is set up per interruption input and sets the interruption level of interruption requests to be handled.
Register list
[bit 4 to 0] ICR4 to 0
The interruption level of the interruption requests that are handled is specified by the interruption level setting
bit. In cases where the interruption level that is set in this register is the same as or more than the level mask
value that is set (has been set) in the ILM register of the CPU, the interruption request is masked at the CPU
side. It is initialized to 11111B on resetting. The settable interruption level setting bit and interruption level are
shown in following Table.
Interruption Level Setting Bit and Interruption Level
Note: ICR 4 is fixed as “1” and can not be written as “0”.
ICR4
ICR3
ICR2
ICR1
ICR0
Interruption level
000000
System reservation
01110
14
01111
15
NMI
1
0
16
Maximum settable level
10001
17
(High)
10010
18
10011
19
10100
20
10101
21
10110
22
10111
23
11000
24
11001
25
11010
26
11011
27
11100
28
11101
29
11110
30
(Low)
1
31
Interruption is prohibited
bit 7
6
5
4
3
2
1
0
R/W
ICR4
ICR3
ICR2
ICR1
R
R/W
ICR0
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