參數(shù)資料
型號: MB91110PMT2
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP144
封裝: PLASTIC, LQFP-144
文件頁數(shù): 75/98頁
文件大?。?/td> 1049K
代理商: MB91110PMT2
MB91110 Series
77
(8) Read/Write Cycle of the Normal DRAM Mode
(VCC5
= 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
*1 : If either the Q1 or A4 cycle is extended for one cycle, the tCYC time needs to be added to this standard.
*2 : Values of this standard are in case of gear cycle
× 1.
If the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing
n with 1/2, 1/4 or 1/8.
Calculation formula : (3 n / 2) × tCYC 20
Parameter
Sym-
bol
Pin Name
Condi-
tions
Value
Unit Remarks
Min
Max
RAS delay time
tCLRAH
CLK
RAS
10
ns
RAS delay time
tCHRAL
10
ns
CAS delay time
tCLCASL
CLK
CAS
10
ns
CAS delay time
tCLCASH
10
ns
ROW address delay time
tCHRAV
CLK
A23 to A00
15
ns
COLUMN address delay time
tCHCAV
15
ns
DW delay time
tCHDWL
CLK
DW
15
ns
DW delay time
tCHDWH
15
ns
Output data delay time
tCHDV1
CLK
D31 to D16
15
ns
RAS
↓ → valid data input time
tRLDV
RAS
D31 to D16
5
/ 2 ×
tCYC
20
ns
*1
*2
CAS
↓ → valid data input time
tCLDV
CAS
D31 to D16
tCYC
17
ns
*1
CAS
↑ → data holding time
tCADH
0
ns
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