參數(shù)資料
型號: MB91F155APFV-G
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP144
封裝: PLASTIC, LQFP-144
文件頁數(shù): 34/108頁
文件大?。?/td> 2523K
代理商: MB91F155APFV-G
MB91350A Series
DS07-16503-5E
31
2.
Internal architecture
The FR-family CPU has a Harvard architecture in which the instruction and data buses are separated. A
32-bit
16-bit bus converter is connected to the 32-bit bus (F-bus), providing an interface between the CPU
and peripheral resources. A Harvard
Princeton bus converter is connected to both the I-bus and D-bus,
providing an interface between the CPU and the bus controller.
FR CPU
Data
RAM
32-bit
16-bit
bus converter
Harvard
Princeton
bus
converter
D-bus
I-bus
D address
I address
External address
External data
D data
Address
Data
16
24
32
I data
R-bus
F-bus
Peripheral resources
Internal I/O
bus controller
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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