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參數(shù)資料
| 型號(hào)： | MB91F155PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 21/103頁 |
| 文件大小： | 866K |
| 代理商： | MB91F155PFV-G |
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MB91F155/MB91154
24
s
s SETTING MODE
1.
Mode Pins
As shown in Table 1 three pins, MD2, 1, and 0 are used to indicate an operation.
Table 1 Mode pins and set modes
2.
Mode Data
The data which the CPU writes to “0000 07FFH” after reset is called mode data.
It is the mode register (MODR) that exists at “0000 07FFH.” Once a mode is set in this register, operations will
take place in that mode. The mode register can be written only once after reset.
The mode specified in the register is enabled immediately after it is written.
[bits 7 and 6] : M1, M0
These are bus mode setting bits. Specify the bus mode to be set to after writing to the mode register.
[bits 5 to 0] :
These bits are reserved for the system.
Mode pin
Mode name
Reset vector
access area
External data
bus width
MD2
MD1
MD0
0
External vector mode 0
External
8 bits
External ROM bus mode
0
1
External vector mode 1
External
16 bits
0
1
0
External vector mode 2
External
32 bits
Not available on this
product type
0
1
External vector mode
Internal
(Mode register)
Single-chip mode
1
Not available
M1
M0
Function
Remarks
0
Single-chip mode
0
1
Internal ROM-external bus mode
1
0
External ROM-external bus mode
11
Setting not allowed
“0” should be written to these bits at all times.
MODR
Initial value Access
Address : 0000 07FFH
XXXXXXXX
W
W : Write only, X : Undefined
M1
M0
Bus mode setting bits
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