參數(shù)資料
型號: MB91F155PFV-G
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP144
封裝: PLASTIC, LQFP-144
文件頁數(shù): 39/103頁
文件大?。?/td> 866K
代理商: MB91F155PFV-G
MB91F155/MB91154
40
(2) Register Descriptions
Port Data Register (PDR)
PDR2 to PDRL are the I/O data registers of the I/O port.
Input/output is controlled with corresponding DDR2 to DDRL.
R/W : Read/Write enabled, X : Undefined,
: Not in use
PDR2
Initial value
Access
Address : 000001H
XXXXXXXXB
R/W
PDR3
Initial value
Access
Address : 000000H
XXXXXXXXB
R/W
PDR4
Initial value
Access
Address : 000007H
XXXXXXXXB
R/W
PDR5
Initial value
Access
Address : 000006H
XXXXXXXXB
R/W
PDR6
Initial value
Access
Address : 000005H
XXXXXXXXB
R/W
PDR8
Initial value
Access
Address : 00000BH
- XXXXXXXB
R/W
PDRC
Initial value
Access
Address : 000013H
XXXXXXXXB
R/W
PDRD
Initial value
Access
Address : 000012H
XXXXXXXXB
R/W
PDRE
Initial value
Access
Address : 000011H
XXXXXXXXB
R/W
PDRF
Initial value
Access
Address : 000010H
- - - XXXXXB
R/W
PDRG
Initial value
Access
Address : 000017H
- - XXXXXXB
R/W
PDRH
Initial value
Access
Address : 000016H
- - XXXXXXB
R/W
PDRI
Initial value
Access
Address : 000015H
- - XXXXXXB
R/W
PDRJ
Initial value
Access
Address : 000014H
- - - - - - 11B
R/W
PDRK
Initial value
Access
Address : 00001BH
XXXXXXXXB
R/W
PDRL
Initial value
Access
Address : 00001AH
XXXXXXXXB
R/W
76
5
4
3
2
1
0
P26
P27
P25
P24
P23
P22
P21
P20
76
5
4
3
2
1
0
P36
P37
P35
P34
P33
P32
P31
P30
76
5
4
3
2
1
0
P46
P47
P45
P44
P43
P42
P41
P40
76
5
4
3
2
1
0
P56
P57
P55
P54
P53
P52
P51
P50
76
5
4
3
2
1
0
P66
P67
P65
P64
P63
P62
P61
P60
76
5
4
3
2
1
0
P86
P85
P84
P83
P82
P81
P80
76
5
4
3
2
1
0
PC6
PC7
PC5
PC4
PC3
PC2
PC1
PC0
76
5
4
3
2
1
0
PD6
PD7
PD5
PD4
PD3
PD2
PD1
PD0
76
5
4
3
2
1
0
PE6
PE7
PE5
PE4
PE3
PE2
PE1
PE0
76
5
4
3
2
1
0
PF4
PF3
PF2
PF1
PF0
76
5
4
3
2
1
0
PG5
PG4
PG3
PG2
PG1
PG0
76
5
4
3
2
1
0
PH5
PH4
PH3
PH2
PH1
PH0
76
5
4
3
2
1
0
PI5
PI4
PI3
PI2
PI1
PI0
76
5
4
3
2
1
0
PJ1
PJ0
76
5
4
3
2
1
0
PK6
PK7
PK5
PK4
PK3
PK2
PK1
PK0
76
5
4
3
2
1
0
PL6
PL7
PL5
PL4
PL3
PL2
PL1
PL0
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