參數(shù)資料
型號: MB91F267NAPMC-GSE1
廠商: Fujitsu Semiconductor America Inc
文件頁數(shù): 24/53頁
文件大?。?/td> 0K
描述: IC MCU FLASH 128KB FLASH 64LQFP
標準包裝: 1
系列: FR MB91265A
核心處理器: FR60Lite RISC
芯體尺寸: 32-位
速度: 33MHz
連通性: CAN,UART/USART
外圍設(shè)備: DMA,WDT
輸入/輸出數(shù): 49
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x8/10b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 64-LQFP
包裝: 托盤
配用: 865-1102-ND - BOARD EVAL RS232 100QFP
其它名稱: 865-1091
33
8183F–AVR–06/12
ATtiny24A/44A/84A
7.
Power Management and Sleep Modes
The high performance and industry leading code efficiency makes the AVR microcontrollers an
ideal choise for low power applications. In addition, sleep modes enable the application to shut
down unused modules in the MCU, thereby saving power. The AVR provides various sleep
modes allowing the user to tailor the power consumption to the application’s requirements.
7.1
Sleep Modes
Figure 6-1 on page 24 presents the different clock systems and their distribution in
ATtiny24A/44A/84A. The figure is helpful in selecting an appropriate sleep mode. Table 7-1
shows the different sleep modes and their wake up sources.
Note:
1. For INT0, only level interrupt.
To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a
SLEEP instruction must be executed. The SM[1:0] bits in the MCUCR Register select which
sleep mode (Idle, ADC Noise Reduction, Standby or Power-down) will be activated by the
SLEEP instruction. See Table 7-2 on page 37 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
Note that if a level triggered interrupt is used for wake-up the changed level must be held for
some time to wake up the MCU (and for the MCU to enter the interrupt service routine). See
7.1.1
Idle Mode
When the SM[1:0] bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the
interrupt system to continue operating. This sleep mode basically halts clk
CPU and clkFLASH, while
allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,
Table 7-1.
Active Clock Domains and Wake-up Sources in Different Sleep Modes
Sleep Mode
Active Clock Domains
Oscillators
Wake-up Sources
clk
CP
U
clk
FLASH
clk
IO
clk
AD
C
Main
Clo
ck
Source
Enab
led
IN
T0
an
d
Pin
Cha
nge
SPM
/EEPROM
Read
y
Interrupt
ADC
In
te
rru
p
t
Other
I/O
W
a
tch
dog
In
te
rru
p
t
Idle
X
XX
ADC Noise Reduction
X
XX
X
Power-down
X
Stand-by
X
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