參數(shù)資料
型號: MB91F267NAPMC-GSE1
廠商: Fujitsu Semiconductor America Inc
文件頁數(shù): 49/53頁
文件大?。?/td> 0K
描述: IC MCU FLASH 128KB FLASH 64LQFP
標準包裝: 1
系列: FR MB91265A
核心處理器: FR60Lite RISC
芯體尺寸: 32-位
速度: 33MHz
連通性: CAN,UART/USART
外圍設備: DMA,WDT
輸入/輸出數(shù): 49
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x8/10b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 64-LQFP
包裝: 托盤
配用: 865-1102-ND - BOARD EVAL RS232 100QFP
其它名稱: 865-1091
56
8183F–AVR–06/12
ATtiny24A/44A/84A
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between and 1 system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in Figure 10-4 on page 56. The out instruction sets the “SYNC LATCH” signal at the
positive edge of the clock. In this case, the delay tpd through the synchronizer is one system
clock period.
Figure 10-4.
Synchronization when Reading a Software Assigned Pin Value
10.1.5
Digital Input Enable and Sleep Modes
As shown in Figure 10-2 on page 54, the digital input signal can be clamped to ground at the
input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep
Controller in Power-down and Standby modes to avoid high power consumption if some input
signals are left floating, or have an analog signal level close to V
CC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt
request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various
other alternate functions as described in “Alternate Port Functions” on page 58.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as
“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt
is not enabled, the corresponding External Interrupt Flag will be set when resuming from the
above mentioned Sleep mode, as the clamping in these sleep mode produces the requested
logic change.
10.1.6
Unconnected Pins
If some pins are unused, it is recommended to ensure that these pins have a defined level. Even
though most of the digital inputs are disabled in the deep sleep modes as described above, float-
ing inputs should be avoided to reduce current consumption in all other modes where the digital
inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
In this case, the pull-up will be disabled during reset. If low power consumption during reset is
out PORTx, r16
nop
in r17, PINx
0xFF
0x00
0xFF
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
t
pd
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MB91F267NPMCR-GE1 制造商:FUJITSU 功能描述: 制造商:FUJITSU 功能描述:MCU 32BIT FR 128K FLASH 64LQFP 制造商:FUJITSU 功能描述:MCU, 32BIT, FR, 128K FLASH, 64LQFP 制造商:FUJITSU 功能描述:MCU, 32BIT, FR, 128K FLASH, 64LQFP, Controller Family/Series:FR60, Core Size:32b 制造商:FUJITSU 功能描述:IC, 32BIT MCU, FR60, 33MHZ, LQFP-64, Controller Family/Series:FR60, Core Size:32bit, No. of I/O's:48, Supply Voltage Min:4V, Supply Voltage Max:5.5V, Digital IC Case Style:LQFP, No. of Pins:64, Program Memory Size:128KB, MSL:- , RoHS Compliant: Yes