參數(shù)資料
型號: MB91F267PFM-G
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP64
封裝: PLASTIC, LQFP-64
文件頁數(shù): 15/53頁
文件大小: 592K
代理商: MB91F267PFM-G
MB91265 Series
22
■ MODE SETTINGS
The FR family uses mode pins (MD2 to MD0) and a mode data to set the operation mode.
1.
Mode Pins
The MD2, MD1, and MD0 pins specify how the mode vector fetch and reset vector fetch is performed.
Setting is prohibited other than that shown in the following table.
2.
Mode data
Data written to the internal mode register (MODR) by a mode vector fetch is called mode data.
After an operation mode has been set in the mode register, the device operates in the operation mode.
The mode data is set by all reset sources. User programs cannot set data to the mode register.
<Details of mode data description>
[bit31 to 24] Reserved bit
Be sure to set this bit to “00000111B”.
Operation is not guaranteed when any value other than “00000111B” is set.
3.
Note
Mode data set in the mode vector must be placed as byte data at 0x000FFFF8.
Use the highest byte from bit 31 to bit 24 for placement as the FR family uses the big endian method for byte
endian.
Mode Pins
Mode name
Reset vector access
area
Remarks
MD2
MD1
MD0
0
Internal ROM mode vector
Internal
0
1
External ROM mode vector
External
Prohibit
31
24 23
16 15
8 7
0
Incorrect 0x000FFFF8
XXXXXXXX
Mode Data
Correct
0x000FFFF8
Mode Data
XXXXXXXX
0x000FFFFC
Reset Vector
31
30
29
28
27
26
25
24
00
01
11
Operation mode setting bits
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