MB91460M Series
2
DS07-16613-2E
Interrupts (save PC/PS) : 6 cycles (16 priority levels)
Harvard architecture enabling program access and data access to be performed simultaneously
Instructions compatible with the FR family
2.
Internal peripheral resources
General-purpose ports : Maximum 175 ports
DMAC (DMA Controller)
Maximum of 5 channels able to operate simultaneously. (External to external : 1 channel)
3 transfer sources (external pin/internal peripheral/software)
Activation source can be selected using software.
Addressing mode specifies full 32-bit addresses (increment/decrement/fixed)
Transfer mode (demand transfer/burst transfer/step transfer/block transfer)
Fly-by transfer support (between external I/O and memory)
Transfer data size selectable from 8/16/32-bit
Multi-byte transfer enabled (by software)
DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H)
A/D converter (successive approximation type)
10-bit resolution: 12 channels
Conversion time: minimum 3
μs
External interrupt inputs : 16 channels
4 channels shared with CAN RX or I2C pins
Bit search module (for REALOS)
Function to search from the MSB (most significant bit) for the position of the first “0”, “1”, or changed bit in a word
LIN-USART (full duplex double buffer): 9 channels
Clock synchronous/asynchronous selectable
Sync-break detection
Internal dedicated baud rate generator
4 channel is equipped with 16 stages of transmission and reception FIFO buffers.
I2C bus interface (supports 400 kbps): 8 channels
Master/slave transmission and reception
Arbitration function, clock synchronization function
CAN controller (C-CAN): 2 channels
Maximum transfer speed: 1 Mbps
32 transmission/reception message buffers
MediaLB
Supports 512Fs
15 channels
Contains local channel buffers: 32 bit
× 2 k.
Contains a 32 bit
× 2 k FIFO buffer for between MediaLB and I2S.
I2S : 10 channels
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