參數(shù)資料
型號： MB91F469GBPB-GSE1
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 88 MHz, RISC MICROCONTROLLER, PBGA320
封裝： 27 X 27 MM, 2.46 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-320
文件頁數(shù)： 21/156頁
文件大?。?/td> 5002K
代理商： MB91F469GBPB-GSE1
MB91460G Series
DS07-16608-1E
117
7.3.
LIN-USART Timings at VDD5 = 3.0 to 5.5 V
Conditions during AC measurements
All AC tests were measured under the following conditions:
- IOdrive = 5 mA
- VDD5 = 3.0 V to 5.5 V, Iload = 3 mA
- VSS5 = 0 V
- Ta =
40 °C to +125 °C
- Cl = 50 pF (load capacity value of pins when testing)
- VOL = 0.2
× VDD5
- VOH = 0.8
× VDD5
- EPILR = 0, PILR = 1 (Automotive Level = worst case)
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA =
40 °C to + 125 °C)
* : Parameter m depends on tSCYCI and can be calculated as :
if tSCYCI = 2*k*tCLKP, then m = k, where k is an integer > 2
if tSCYCI = (2*k + 1)*tCLKP, then m = k + 1, where k is an integer > 1
Notes :
The above values are AC characteristics for CLK synchronous mode.
tCLKP is the cycle time of the peripheral clock.
Parameter
Symbol
Pin name
Condition
VDD5 = 3.0 V to 4.5 V VDD5 = 4.5 V to 5.5 V
Unit
Min
Max
Min
Max
Serial clock
cycle time
tSCYCI
SCKn
Internal
clock
operation
(master
mode)
4 tCLKP
4 tCLKP
ns
SCK
↓ → SOT
delay time
tSLOVI
SCKn
SOTn
30
30
20
ns
SOT
→ SCK ↓
delay time
tOVSHI
SCKn
SOTn
m
×
tCLKP
30*
m
×
tCLKP
20*
ns
Valid SIN
→
SCK
↑ setup time
tIVSHI
SCKn
SINn
tCLKP + 55
tCLKP + 45
ns
SCK
↑ → valid
SIN hold time
tSHIXI
SCKn
SINn
0
0
ns
Serial clock
“H” pulse width
tSHSLE
SCKn
External
clock
operation
(slave
mode)
tCLKP + 10
tCLKP + 10
ns
Serial clock
“L” pulse width
tSLSHE
SCKn
tCLKP + 10
tCLKP + 10
ns
SCK
↓ → SOT
delay time
tSLOVE
SCKn
SOTn
2 tCLKP +
55
2 tCLKP + 45
ns
Valid SIN
→
SCK
↑ setup time
tIVSHE
SCKn
SINn
10
10
ns
SCK
↑ → valid
SIN hold time
tSHIXE
SCKn
SINn
tCLKP + 10
tCLKP + 10
ns
SCK rising time
tFE
SCKn
20
20
ns
SCK falling time
tRE
SCKn
20
20
ns
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