參數(shù)資料
型號： MB91F469GBPB-GSE1
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 88 MHz, RISC MICROCONTROLLER, PBGA320
封裝： 27 X 27 MM, 2.46 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-320
文件頁數(shù)： 83/156頁
文件大?。?/td> 5002K
代理商： MB91F469GBPB-GSE1
MB91460G Series
32
DS07-16608-1E
6.
Mode pins (MD_x)
These pins should be connected directly to the power supply or ground pins. To prevent the device from entering
test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and power
supply pin or ground pin on the printed circuit board as possible and connect them with low impedance.
7.
Notes on operating in PLL clock mode
If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may
continue to operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this self-
running operation cannot be guaranteed.
8.
Pull-up control
The AC standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin.
9.
Notes on PS register
As the PS register is processed in advance by some instructions, when the debugger is being used, the exception
handling may result in execution breaking in an interrupt handling routine or the displayed values of the flags in
the PS register being updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,
the operation before and after the EIT always proceeds according to specification.
The following behavior may occur if any of the following occurs in the instruction
immediately after a DIV0U/DIV0S instruction:
(a) a user interrupt or NMI is accepted;
(b) single-step execution is performed;
(c) execution breaks due to a data event or from the emulator menu.
1. D0 and D1 flags are updated in advance.
2. An EIT handling routine (user interrupt/NMI or emulator) is executed.
3. Upon returning from the EIT, the DIV0U/DIV0S instruction is executed
and the D0 and D1 flags are updated to the same values as those in 1.
The following behavior occurs when an ORCCR, STILM, MOV Ri,PS instruction is executed
to enable a user interrupt or NMI source while that interrupt is in the active state.
1. The PS register is updated in advance.
2. An EIT handling routine (user interrupt/NMI or emulator) is executed.
3. Upon returning from the EIT, the above instructions are executed and the PS register
is updated to the same value as in 1.
相關PDF資料
PDF描述
MB91F469GAPB-GS 32-BIT, FLASH, 88 MHz, RISC MICROCONTROLLER, PBGA320
MB91F469GBPB-GS 32-BIT, FLASH, 88 MHz, RISC MICROCONTROLLER, PBGA320
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