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參數(shù)資料
| 型號： | MB91FV130CR-ES |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, CPGA299 |
| 封裝： | CERAMIC, PGA-299 |
| 文件頁數(shù)： | 19/123頁 |
| 文件大?。?/td> | 1331K |
| 代理商： | MB91FV130CR-ES |
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MB91133/MB91F133
115
Other instructions (16 instructions)
*1: In the ADDSP instruction, the reference between u8 of TYPE-D in the instruction format and assembler
description s10 is as follows.
s10
→ s8 = s10>>2
*2: In the ENTER instruction, the reference between i8 of TYPE-C in the instruction format and assembler
description u10 is as follows.
u10
→ u8 = u10>>2
*3: If either of R0 to R7 is specified in reglist, assembler generates LDM0. If either of R8 to R15 is specified,
assembler generates LDM1. Both LDM0 and LDM1 may be generated.
*4: The number of cycles needed for execution of LDM0 (reglist) and LDM1 (reglist) is given by the following
calculation; a
× (n – 1) + b + 1 when “n” is number of registers specified.
*5: If either of R0 to R7 is specified in reglist, assembler generates STM0. If either of R8 to R15 is specified,
assembler generates STM1. Both STM0 and STM1 may be generated.
*6: The number of cycles needed for execution of STM0 (reglist) and STM1 (reglist) is given by the following
calculation; a
× n + 1 when “n” is number of registers specified.
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
NOP
E
9F – A
1
– – – – No changes
ANDCCR #u8
ORCCR
#u8
D
83
93
c
CCCC
CCR and u8
→ CCR
CCR or u8
→ CCR
STILM
#u8
D
87
1
– – – – i8
→ ILM
Set ILM immediate
value
ADDSP
#s10
*1
D
A3
1
– – – – R15 + = s10
ADD SP instruction
EXTSB
Ri
EXTUB
Ri
EXTSH
Ri
EXTUH
Ri
E
97 – 8
97 – 9
97 – A
97 – B
1
––––
Sign extension 8
→ 32 bits
Zero extension 8
→ 32 bits
Sign extension 16
→ 32 bits
Zero extension 16
→ 32 bits
LDM0
(reglist)
LDM1
(reglist)
* LDM
(reglist)
*3
D
8C
8D
*4
–
––––
(R15)
→ reglist,
R15 increment
(R15)
→ reglist,
R15 increment
(R15 + +)
→ reglist,
Load-multi R0 to R7
Load-multi R8 to R15
Load-multi R0 to R15
STM0
(reglist)
STM1
(reglist)
* STM2
(reglist)
*5
D
8E
8F
*6
–
––––
R15 decrement,
reglist
→ (R15)
R15 decrement,
reglist
→ (R15)
reglist
→ (R15 + +)
Store-multi R0 to R7
Store-multi R8 to R15
Store-multi R0 to R15
ENTER
#u10
*2
D
0F
1+a
–––– R14
→ (R15 – 4),
R15 – 4
→ R14,
R15 – u10
→ R15
Entrance processing
of function
LEAVE
E
9F – 9
b
– – – – R14 + 4
→ R15,
(R15 – 4)
→ R14
Exit processing of
function
XCHB
@Rj, Ri
A
8A
2a
– – – – Ri
→ TEMP,
(Rj)
→ Ri,
TEMP
→ (Rj)
For SEMAFO
management
Byte data
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB91FV310A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Proprietary 32-bit Microcontroller CMOS |
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| MB91FV319A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91FV319APMT-ES | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91FV319R | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontrollers |
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