參數(shù)資料
型號： MB95107BBGL
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 16.25 MHz, MICROCONTROLLER, PBGA96
封裝： 6 X 6 MM, 1.30 MM HEIGHT, 0.50 MM PITCH, PLASTIC, FBGA-96
文件頁數(shù)： 54/80頁
文件大小： 2746K
代理商： MB95107BBGL
MB95100B Series
58
DS07-12617-3E
(8) I2C Timing
(VCC
= 3.3 V, AVSS = VSS = 0.0 V, TA = 40 °C to + 85 °C)
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal.
*3 : A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement
tSU;DAT
≥ 250 ns must then be met.
Parameter
Symbol
Pin name
Condition
Value
Unit
Standard-mode
Fast-mode
Min
Max
Min
Max
SCL clock frequency
fSCL
SCL0
R
= 1.7 kΩ,
C
= 50 pF*1
0
100
0
400
kHz
(Repeat) Start condition hold
time SDA
↓ → SCL ↓
tHD;STA
SCL0
SDA0
4.0
0.6
μs
SCL clock “L” width
tLOW
SCL0
4.7
1.3
μs
SCL clock “H” width
tHIGH
SCL0
4.0
0.6
μs
(Repeat) Start condition set-
up time SCL
↑ → SDA ↓
tSU;STA
SCL0
SDA0
4.7
0.6
μs
Data hold time SCL
↓ → SDA
↓ ↑
tHD;DAT
SCL0
SDA0
03.45*2
00.9*3
μs
Data setup time SDA
↓ ↑ →
SCL
↑
tSU;DAT
SCL0
SDA0
0.25
0.1
μs
Stop condition setup time SCL
↑ → SDA ↑
tSU;STO
SCL0
SDA0
4
0.6
μs
Bus free time between stop
condition and start condition
tBUF
SCL0
SDA0
4.7
1.3
μs
SDA0
SCL0
tWAKEUP
tHD;STA
tSU;DAT
tHD;STA
tSU;STA
tLOW
tHD;DAT
tHIGH
tSU;STO
tBUF
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