Sampling at the falling edge of sampling clock*1 and prohibited seria" />
參數(shù)資料
型號(hào): MB95F128DPF-GE1
廠商: Fujitsu Semiconductor America Inc
文件頁(yè)數(shù): 47/67頁(yè)
文件大?。?/td> 0K
描述: IC MCU FLASH 60K ROM 100QFP
標(biāo)準(zhǔn)包裝: 1
系列: F²MC MB95120
核心處理器: F²MC-8FX
芯體尺寸: 8-位
速度: 16MHz
連通性: I²C,LIN,SIO,UART/USART
外圍設(shè)備: LCD,LVD,POR,PWM,WDT
輸入/輸出數(shù): 87
程序存儲(chǔ)器容量: 60KB(60K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.3 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x8/10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-QFP
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 722 (CN2011-ZH PDF)
其它名稱: 865-1073
MB95120 Series
51
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit
= 1, ECCR register : SCDE bit = 0)
(VCC
= 3.3 V, AVSS = VSS = 0.0 V, TA = 40 °C to + 85 °C)
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
Parameter
Sym-
bol
Pin name
Conditions
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK
Internal clock
operation output pin :
CL
= 80 pF + 1 TTL.
5 tMCLK*3
ns
SCK
↑ → SOT delay time
tSHOVI
SCK, SOT
95
+95
ns
Valid SIN
→ SCK ↓
tIVSLI
SCK, SIN
tMCLK*3
+ 190
ns
SCK
↓ → valid SIN hold time
tSLIXI
SCK, SIN
0
ns
Serial clock “H” pulse width
tSHSL
SCK
External clock
operation output pin :
CL
= 80 pF + 1 TTL.
3 tMCLK*3
tR
ns
Serial clock “L” pulse width
tSLSH
SCK
tMCLK*3
+ 95
ns
SCK
↑ → SOT delay time
tSHOVE
SCK, SOT
2 tMCLK*3
+ 95
ns
Valid SIN
→ SCK ↓
tIVSLE
SCK, SIN
190
ns
SCK
↓ → valid SIN hold time
tSLIXE
SCK, SIN
tMCLK*3
+ 95
ns
SCK fall time
tF
SCK
10
ns
SCK rise time
tR
SCK
10
ns
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