(VCC = 3.3 V, AVSS
參數(shù)資料
型號(hào): MB95F128DPF-GE1
廠商: Fujitsu Semiconductor America Inc
文件頁(yè)數(shù): 53/67頁(yè)
文件大小: 0K
描述: IC MCU FLASH 60K ROM 100QFP
標(biāo)準(zhǔn)包裝: 1
系列: F²MC MB95120
核心處理器: F²MC-8FX
芯體尺寸: 8-位
速度: 16MHz
連通性: I²C,LIN,SIO,UART/USART
外圍設(shè)備: LCD,LVD,POR,PWM,WDT
輸入/輸出數(shù): 87
程序存儲(chǔ)器容量: 60KB(60K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.3 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x8/10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-QFP
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 722 (CN2011-ZH PDF)
其它名稱: 865-1073
MB95120 Series
57
(Continued)
(VCC
= 3.3 V, AVSS = VSS = 0.0 V, TA = 40 °C to + 85 °C)
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 :
Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
m is CS4 bit and CS3 bit (bit 4 and bit 3) of I2C clock control register (ICCR) .
n is CS2 bit to CS0 bit (bit 2 to bit 0) of I2C clock control register (ICCR) .
Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of
ICCR0 register.
Standard-mode :
m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n)
= (1, 8)
: 0.9 MHz < tMCLK
≤ 1 MHz
(m, n)
= (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz
(m, n)
= (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz
(m, n)
= (1, 98)
: 0.9 MHz < tMCLK
≤ 10 MHz
Fast-mode :
m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n)
= (1, 8)
: 3.3 MHz < tMCLK
≤ 4 MHz
(m, n)
= (1, 22) , (5, 4)
: 3.3 MHz < tMCLK
≤ 8 MHz
(m, n)
= (6, 4)
: 3.3 MHz < tMCLK
≤ 10 MHz
Parameter
Sym-
bol
Pin
name
Condi-
tions
Value*2
Unit
Remarks
Min
Max
Stop condition
detection
tSU;STO
SCL0
SDA0
R
= 1.7 k,
C
= 50 pF*1
2 tMCLK
20
ns
Undetected when
1 tMCLK is used at
reception
Restart condition
detection condition
tSU;STA
SCL0
SDA0
2 tMCLK
20
ns
Undetected when
1 tMCLK is used at
reception
Bus free time
tBUF
SCL0
SDA0
2 tMCLK
20
ns
At reception
Data hold time
tHD;DAT
SCL0
SDA0
2 tMCLK
20
ns
At slave transmission
mode
Data setup time
tSU;DAT
SCL0
SDA0
tLOW
3 tMCLK 20
ns
At slave transmission
mode
Data hold time
tHD;DAT
SCL0
SDA0
0
ns
At reception
Data setup time
tSU;DAT
SCL0
SDA0
tMCLK
20
ns
At reception
SDA
↓→SCL↑
(at wakeup function)
tWAKE-
UP
SCL0
SDA0
Oscillation
stabilization
wait time
+
2 tMCLK
20
ns
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