(VCC = 3.3 V, AV
參數(shù)資料
型號: MB95F128DPMC-GE1
廠商: Fujitsu Semiconductor America Inc
文件頁數(shù): 43/67頁
文件大小: 0K
描述: IC MCU FLASH 60K ROM 100LQFP
標(biāo)準(zhǔn)包裝: 1
系列: F²MC MB95120
核心處理器: F²MC-8FX
芯體尺寸: 8-位
速度: 16MHz
連通性: I²C,LIN,SIO,UART/USART
外圍設(shè)備: LCD,LVD,POR,PWM,WDT
輸入/輸出數(shù): 87
程序存儲器容量: 60KB(60K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.3 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x8/10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
其它名稱: 865-1072
MB95120 Series
48
(6) UART/SIO, Serial I/O Timing
(VCC
= 3.3 V, AVSS = VSS = 0.0 V, TA = 40 °C to + 85 °C)
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
Parameter
Symbol
Pin name
Conditions
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
UCK0
Internal clock
operation output pin :
CL
= 80 pF + 1TTL.
4 tMCLK*
ns
UCK
↓ → UO time
tSLOV
UCK0, UO0
190
+190
ns
Valid UI
→ UCK ↑
tIVSH
UCK0, UI0
2 tMCLK*
ns
UCK
↑ → valid UI hold time
tSHIX
UCK0, UI0
2 tMCLK*
ns
Serial clock “H” pulse width
tSHSL
UCK0
External clock
operation output pin :
CL
= 80 pF + 1TTL.
4 tMCLK*
ns
Serial clock “L” pulse width
tSLSH
UCK0
4 tMCLK*
ns
UCK
↓ → UO time
tSLOV
UCK0, UO0
0
190
ns
Valid UI
→ UCK ↑
tIVSH
UCK0, UI0
2 tMCLK*
ns
UCK
↑ → valid UI hold time
tSHIX
UCK0, UI0
2 tMCLK*
ns
tSCYC
tIVSH
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSHIX
tSLOV
0.8 V
2.4 V
0.8 V
2.4 V
UCK0
UO0
UI0
0.8 V
tSLSH
tIVSH
tSHIX
tSLOV
0.2 VCC 0.2 VCC
0.8 VCC 0.8 VCC
tSHSL
2.4 V
UCK0
UO0
UI0
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
Internal shift clock mode
External shift clock mode
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