參數(shù)資料
型號(hào)： MB95F128TPF
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù)： 44/66頁(yè)
文件大?。?/td> 824K
代理商： MB95F128TPF
MB95120H Series
49
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit
= 1, ECCR register : SCDE bit = 0)
(VCC
= 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = 40 °C to + 85 °C)
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
Parameter
Sym-
bol
Pin name
Conditions
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK
Internal clock
operation output pin :
CL
= 80 pF + 1 TTL.
5 tMCLK*3
ns
SCK
↑ → SOT delay time
tSHOVI
SCK, SOT
95
+95
ns
Valid SIN
→ SCK ↓
tIVSLI
SCK, SIN
tMCLK*3
+ 190
ns
SCK
↓ → valid SIN hold time
tSLIXI
SCK, SIN
0
ns
Serial clock “H” pulse width
tSHSL
SCK
External clock
operation output pin :
CL
= 80 pF + 1 TTL.
3 tMCLK*3
tR
ns
Serial clock “L” pulse width
tSLSH
SCK
tMCLK*3
+ 95
ns
SCK
↑ → SOT delay time
tSHOVE
SCK, SOT
2 tMCLK*3
+ 95
ns
Valid SIN
→ SCK ↓
tIVSLE
SCK, SIN
190
ns
SCK
↓ → valid SIN hold time
tSLIXE
SCK, SIN
tMCLK*3
+ 95
ns
SCK fall time
tF
SCK
10
ns
SCK rise time
tR
SCK
10
ns
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