參數(shù)資料
型號： MB95F378LPMC2-G-SNE2
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PQFP64
封裝： 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 60/76頁
文件大?。?/td> 2597K
代理商： MB95F378LPMC2-G-SNE2
MB95310L/370L Series
DS07-12628-1E
63
(VCC = 3.0 V
±10%, AVSS = VSS = 0.0 V, TA = 40°C to +85°C)
(Continued)
Parameter Symbol Pin name Conditions
Value*2
Unit
Remarks
Min
Max
Setup time
between
clearing
interrupt
and SCL
rising
tSU;INT
SCL0
R = 1.7 k
Ω,
C = 50 pF*1
(nm / 2)tMCLK
20
(1
+ nm / 2)tMCLK + 20 ns
Minimum
value is
applied to
interrupt at
9th SCL
↓.
Maximum
value is
applied to
interrupt at
8th SCL
↓.
SCL clock
“L” width
tLOW
SCL0
4 tMCLK
20
—
ns
At reception
SCL clock
“H” width
tHIGH
SCL0
4 tMCLK
20
—
ns
At reception
Start
condition
detection
tHD;STA
SCL0,
SDA0
2 tMCLK
20
—ns
Not detected
when 1 tMCLK
is used at
reception
Stop
condition
detection
tSU;STO
SCL0,
SDA0
2 tMCLK
20
—ns
Not detected
when 1 tMCLK
is used at
reception
Restart
condition
detection
condition
tSU;STA
SCL0,
SDA0
2 tMCLK
20
—ns
Not detected
when 1 tMCLK
is used at
reception
Bus free
time
tBUF
SCL0,
SDA0
2 tMCLK
20
—
ns
At reception
Data hold
time
tHD;DAT
SCL0,
SDA0
2 tMCLK
20
—ns
At slave
transmission
mode
Data setup
time
tSU;DAT
SCL0,
SDA0
tLOW
3 tMCLK 20
—ns
At slave
transmission
mode
Data hold
time
tHD;DAT
SCL0,
SDA0
0
—
ns
At reception
Data setup
time
tSU;DAT
SCL0,
SDA0
tMCLK
20
—
ns
At reception
SDA
↓→
SCL
↑
(at wakeup
function)
tWAKEUP
SCL0,
SDA0
Oscillation
stabilization wait
time
+ 2 tMCLK 20
—ns
相關(guān)PDF資料
PDF描述
MB95F376EPMC1-G-SNE2 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PQFP64
MB95F374EPMC1-G-SNE2 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PQFP64
MB95F398HPMC-G-SNE2 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PQFP48
MB95F394KPMC-G-SNE2 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PQFP48
MB95F398KWQN-G-SNE1 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PQCC48
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