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參數(shù)資料
| 型號(hào)： | MB95F414HPMC-G-SNE2 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 42/76頁 |
| 文件大?。?/td> | 3707K |
| 代理商： | MB95F414HPMC-G-SNE2 |
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MB95410H/470H Series
DS702-00004-0v01-E
47
2.
Recommended Operating Conditions
(VSS = 0.0 V)
*1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range.
*2: The value is initially 2.88 V when the low-voltage detection reset is used.
*3: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for
the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see
the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise,
minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing
the layout of a printed circuit board.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Parameter
Symbol
Value
Unit
Remarks
Min
Max
Power supply
voltage
VCC,
AVCC
2.4*1*2
5.5*1
V
In normal operation
Other than on-chip debug
mode
2.3
5.5
Hold condition in stop mode
2.9
5.5
In normal operation
On-chip debug mode
2.3
5.5
Hold condition in stop mode
Smoothing
capacitor
CS
0.022
1
F
*3
Operating
temperature
TA
40
+ 85
° C
Other than on-chip debug mode
+ 5
+ 35
On-chip debug mode
C
Cs
DBG
*
Since the DBG pin becomes a communication pin in on-chip debug mode,
set a pull-up resistor value suiting the input/output specifications of P12/DBG.
*:
RST
DBG / RST / C pins connection diagram
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