參數(shù)資料
型號： MB95F478KPMC1-G-SNE2
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP64
封裝： 10 X10 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 50/76頁
文件大?。?/td> 3707K
代理商： MB95F478KPMC1-G-SNE2
MB95410H/470H Series
54
DS702-00004-0v01-E
(2) Source Clock/Machine Clock
(VCC = 5.0 V
± 10%, VSS = 0.0 V, TA = 40° C to +85° C)
*1: This is the clock before it is divided according to the division ratio set by the machine clock divide ratio select
bits (SYCC:DIV1, DIV0). This source clock is divided to become a machine clock according to the division
ratio set by the machine clock divide ratio select bits (SYCC:DIV1, DIV0). In addition, a source clock can be
selected from the following.
Main clock divided by 2
PLL multiplication of main clock (select from 2, 2.5, 4 multiplication)
Main CR clock divided by 2
Subclock divided by 2
Sub-CR clock divided by 2
(Continued)
Parameter
Symbol
Pin
name
Value
Unit
Remarks
Min
Typ
Max
Source clock
cycle time*1
tSCLK
—
61.5
—
2000
ns
When the main oscillation clock is used
Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
61.5
—
2000
ns
When the main oscillation clock is used
Min: FCH = 8.125 MHz, multiplied by the
PLL multiplier of 2
Max: FCH = 1 MHz, divided by 2
80
—
1000
ns
When the main CR clock is used
Min: FCRH = 12.5 MHz
Max: FCRH = 1 MHz
—61
—
s
When the sub-oscillation clock is used
FCL = 32.768 kHz, divided by 2
—20
—
s
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
Source clock
frequency
FSP
—
0.50
—
16.25
MHz When the main oscillation clock is used
1
—
12.5
MHz When the main CR clock is used
FSPL
—
16.384
—
kHz When the sub-oscillation clock is used
—
50
—
kHz
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
Machine clock
cycle time*2
(minimum
instruction
execution
time)
tMCLK
—
61.5
—
32000
ns
When the main oscillation clock is used
Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
80
—
16000
ns
When the main CR clock is used
Min: FSP = 12.5 MHz
Max: FSP = 1 MHz, divided by 16
61
—
976.5
s
When the sub-oscillation clock is used
Min: FSPL = 16.384 kHz, no division
Max: FSPL = 16.384 kHz, divided by 16
20
—
320
s
When the sub-CR clock is used
Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
Machine clock
frequency
FMP
—
0.031
—
16.25
MHz When the main oscillation clock is used
0.0625
—
12.5
MHz When the main CR clock is used
FMPL
1.024
—
16.384
kHz When the sub-oscillation clock is used
3.125
—
50
kHz
When the sub-CR clock is used
FCRL = 100 kHz
相關PDF資料
PDF描述
MB95F476HPMC1-G-SNE2 MICROCONTROLLER, PQFP64
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