參數(shù)資料
型號： MB95F564KPFT-G-JNE2
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PDSO20
封裝： 4.40 X 6.50 MM, 1.20 MM HEIGHT, 0.65 MM PITCH, PLASTIC, TSSOP-20
文件頁數(shù)： 32/84頁
文件大小： 3941K
代理商： MB95F564KPFT-G-JNE2
MB95560H/570H/580H Series
38
DS702-00010-2v0-E
(Continued)
R/W access symbols
Initial value symbols
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
Address
Register
abbreviation
Register name
R/W Initial value
0F89H
to
0F91H
—
(Disabled)
—
0F92H
T01CR0
8/16-bit composite timer 01 status control register 0
R/W
00000000B
0F93H
T00CR0
8/16-bit composite timer 00 status control register 0
R/W
00000000B
0F94H
T01DR
8/16-bit composite timer 01 data register
R/W
00000000B
0F95H
T00DR
8/16-bit composite timer 00 data register
R/W
00000000B
0F96H
TMCR0
8/16-bit composite timer 00/01 timer mode control register
R/W
00000000B
0F97H
to
0FBBH
—
(Disabled)
—
0FBCH
BGR1
LIN-UART baud rate generator register 1
R/W
00000000B
0FBDH
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH
to
0FC2H
—
(Disabled)
—
0FC3H
AIDRL
A/D input disable register (Lower)
R/W
00000000B
0FC4H
to
0FE3H
—
(Disabled)
—
0FE4H
CRTH
Main CR clock trimming register (upper)
R/W
000XXXXXB
0FE5H
CRTL
Main CR clock trimming register (lower)
R/W
000XXXXXB
0FE6H
—
(Disabled)
—
0FE7H
CRTDA
Main CR clock temperature dependent adjustment
R/W
00011111B
0FE8H
SYSC
System configuration register
R/W
11000011B
0FE9H
CMCR
Clock monitoring control register
R/W
00000000B
0FEAH
CMDR
Clock monitoring data register
R/W
00000000B
0FEBH
WDTH
Watchdog timer selection ID register (upper)
R/W XXXXXXXXB
0FECH
WDTL
Watchdog timer selection ID register (lower)
R/W XXXXXXXXB
0FEDH
to
0FFFH
—
(Disabled)
—
R/W
: Readable / Writable
R
: Read only
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is undefined.
相關(guān)PDF資料
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MB95F583KPFT-G-JNE2 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PDSO16
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