參數(shù)資料
型號(hào)： MB95F564KPFT-G-JNE2
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PDSO20
封裝： 4.40 X 6.50 MM, 1.20 MM HEIGHT, 0.65 MM PITCH, PLASTIC, TSSOP-20
文件頁(yè)數(shù)： 52/84頁(yè)
文件大?。?/td> 3941K
代理商： MB95F564KPFT-G-JNE2
MB95560H/570H/580H Series
56
DS702-00010-2v0-E
(6) LIN-UART Timing (only available on MB95F562H/F562K/F563H/F563K/F564H/F564K/F582H/F582K/
F583H/F583K/F584H/F584K)
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register: SCES bit = 0, ECCR register: SCDE bit = 0)
(VCC = 5.0 V
± 10%, AVSS = VSS = 0.0 V, TA = 40°C to + 85°C)
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
Parameter
Symbol Pin name
Condition
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK
Internal clock
operation output pin:
CL = 80 pF
+ 1 TTL
5 tMCLK*3
—ns
SCK
↓→ SOT delay time
tSLOVI
SCK, SOT
50
+ 50
ns
Valid SIN
→ SCK ↑
tIVSHI
SCK, SIN
tMCLK*3
+ 80
—
ns
SCK
↑→ valid SIN hold time
tSHIXI
SCK, SIN
0
—
ns
Serial clock “L” pulse width
tSLSH
SCK
External clock
operation output pin:
CL = 80 pF
+ 1 TTL
3 tMCLK*3
tR
—ns
Serial clock “H” pulse width
tSHSL
SCK
tMCLK*3
+ 10
—
ns
SCK
↓→ SOT delay time
tSLOVE
SCK, SOT
—
2 tMCLK*3
+ 60 ns
Valid SIN
→ SCK ↑
tIVSHE
SCK, SIN
30
—
ns
SCK
↑→ valid SIN hold time
tSHIXE
SCK, SIN
tMCLK*3
+ 30
—
ns
SCK fall time
tF
SCK
—
10
ns
SCK rise time
tR
SCK
—
10
ns
相關(guān)PDF資料
PDF描述
MB95F583KPFT-G-JNE2 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PDSO16
MB95F562HPF-G-JNE2 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PDSO20
MB95F584KPF-G-JNE2 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PDSO16
MB95F573HPF-G-JNE2 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PDSO8
MB95F582KWQN-G-JNERE1 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PQCC32
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