參數(shù)資料
型號(hào): MB95F564KWQN-G-JNERE1
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PQCC32
封裝: 5 X 5 MM, 0.80 MM HEIGHT, PLASTIC, QFN-32
文件頁數(shù): 54/84頁
文件大?。?/td> 3941K
代理商: MB95F564KWQN-G-JNERE1
MB95560H/570H/580H Series
58
DS702-00010-2v0-E
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register: SCES bit = 1, ECCR register: SCDE bit = 0)
(VCC = 5.0 V
± 10%, VSS = 0.0 V, TA = 40°C to + 85°C)
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
Parameter
Symbol Pin name
Condition
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK
Internal clock
operation output pin:
CL = 80 pF
+ 1 TTL
5 tMCLK*3
—ns
SCK
↑→ SOT delay time
tSHOVI
SCK, SOT
50
+ 50
ns
Valid SIN
→ SCK ↓
tIVSLI
SCK, SIN
tMCLK*3
+ 80
ns
SCK
↓→ valid SIN hold time
tSLIXI
SCK, SIN
0
ns
Serial clock “H” pulse width
tSHSL
SCK
External clock
operation output pin:
CL = 80 pF
+ 1 TTL
3 tMCLK*3
tR
—ns
Serial clock “L” pulse width
tSLSH
SCK
tMCLK*3
+ 10
ns
SCK
↑→ SOT delay time
tSHOVE
SCK, SOT
2 tMCLK*3
+ 60 ns
Valid SIN
→ SCK ↓
tIVSLE
SCK, SIN
30
ns
SCK
↓→ valid SIN hold time
tSLIXE
SCK, SIN
tMCLK*3
+ 30
ns
SCK fall time
tF
SCK
10
ns
SCK rise time
tR
SCK
10
ns
相關(guān)PDF資料
PDF描述
MB95F564HWQN-G-JNERE1 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PQCC32
MB95F583KPF-G-JNE2 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PDSO16
MB95F564HPF-G-JNE2 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PDSO20
MB95F572KPF-G-JNE2 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PDSO8
MB95F582KPFT-G-JNE2 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PDSO16
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