參數(shù)資料
型號： MB95F572HPF-G-JNE2
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PDSO8
封裝： 5.30 X 5.24 MM, 2.10 MM HEIGHT, 1.27 MM PITCH, PLASTIC, M08, SOP-8
文件頁數(shù)： 57/84頁
文件大?。?/td> 3929K
代理商： MB95F572HPF-G-JNE2
MB95560H/570H/580H Series
60
DS702-00010-1v0-E
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register: SCES bit = 0, ECCR register: SCDE bit = 1)
(VCC = 5.0 V
± 10%, VSS = 0.0 V, TA = 40°C to + 85°C)
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock.
Parameter
Symbol Pin name
Condition
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK
Internal clock
operation output pin:
CL = 80 pF
+ 1 TTL
5 tMCLK*3
—ns
SCK
↑→ SOT delay time
tSHOVI
SCK, SOT
50
+ 50
ns
Valid SIN
→ SCK ↓
tIVSLI
SCK, SIN
tMCLK*3
+ 80
—
ns
SCK
↓→ valid SIN hold time
tSLIXI
SCK, SIN
0
—
ns
SOT
→ SCK ↓ delay time
tSOVLI
SCK, SOT
3 tMCLK*3
70
—
ns
0.8 VCC
0.2 VCC
tSHOVI
tSOVLI
tIVSLI
tSLIXI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SCK
SOT
SIN
0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
tSCYC
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