參數(shù)資料
型號(hào)： MB98D81223
廠商： Fujitsu Limited
英文描述： 3V Only 4M Bits Flash Miniature Cards(單3V 4M 微型閃存卡)
中文描述： 3V時(shí)僅4分位閃存微型卡（單3V的分微型閃存卡）
文件頁數(shù)： 9/46頁
文件大小： 446K
代理商： MB98D81223
9
MB98D81123/81223-15
I
FUNCTION DESCRIPTIONS
1. Read Mode
The data in the common can be read with “OE#=VIL” and “WE#=VIH”. The address is selected with A0-A20.
And CEL# and CEH# select output mode.
2. Standby Mode
– CEL# and CEH# at “VIH” place the card in Standby mode. D0-D15 are placed in a high-Z state independent
of the status “OE#” and “WE#”.
3. Output Disable Mode
– The outputs are disabled with OE# and WE# at “VIH”. D0-D15 are placed in high-Z state.
4. Write Mode
1) Common Memory Write
– The card is in Write mode with “OE#=VIH” and “WE# and CE#=VIL”.
– Commands can be written at the Write mode.
– Two types of the Write mode, “WE# control” and “CE# control” are available.
5. Command Definitions
– User can select the card operation by writing the specific address and data sequences into the command
register. If incollect address and data are written or improper sequence is done, the card is reseted to read
mode. See “COMMAND DEFINISION TABLE”.
6.
Automated Program Capability
– Programming operation can switch the data from “1” to “0”.
– The data is programmed on a byte-by-byte or word-by-word basis.
– The card will automatically provide adequate internally generated programming pulses and verify the pro-
grammed cell margin by writing four bus cycle operation. The card returns to Common Memory Read mode
automatically after the programming is completed.
– Addresses are latched at falling edge of WE# or CE# and data is latched at rising edge of WE# or CE#. The
fourth rising edge of WE# or CE# on the command write cycle begins programming operation.
– We can check whether a byte (word) programming operation is completed successfully by sequence flug with
BUSY#, Data# Polling or Toggle Bit function. See “WRITE OPERATION STATUS”.
– Any commands written to the chip during programming operation will be ignored.
7. Automated Chip Erase Capability
– We can execute chip erase operation by 6 bus cycle operation. Chip erase does not require the user to program
the chip prior to erase. Upon executing the Erase command sequence the chip automatically will program
and verify the entire memory for an all zero data pattern prior to electrical erase. The system is not required
to provide any controls or timing during these operations.
– The card returns to Common Memory Read mode automatically after the chip erasing is completed.
– Whether or not chip erase operation is completed successfully can be checked by sequence flug with BUSY#,
Data# Polling or Toggle Bit function. See “WRITE OPERATION STATUS”.
– Any commands written to the chip during programming operation will be ignored.
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