參數(shù)資料
型號: MBM29DL324TE12PBT
廠商: FUJITSU LTD
元件分類: DRAM
英文描述: 32M (4M x 8/2M x 16) BIT Dual Operation
中文描述: 2M X 16 FLASH 3V PROM, 120 ns, PBGA63
封裝: PLASTIC, FBGA-63
文件頁數(shù): 43/80頁
文件大?。?/td> 1588K
代理商: MBM29DL324TE12PBT
MBM29DL32XTE/BE
-80/90/12
43
Hidden ROM (Hi-ROM) Protect Command
There are two methods to protect the Hidden ROM area. One is to write the sector group protect setup com-
mand(60h), set the sector address in the Hidden ROM area and (A
6
, A
1
, A
0
) = (0,1,0), and write the sector group
protect command(60h) during the Hidden ROM mode. The same command sequence could be used because
except that it is in the Hidden ROM mode and that it does not apply high voltage to RESET pin, it is the same
as the extension sector group protect in the past. Please refer to “Function Explanation
Extended Command
(3) Extended Sector Group Protection” for details of extension sector group protect setting.
The other is to apply high voltage (V
ID
) to A
9
and OE, set the sector address in the Hidden ROM area and (A
6
,
A
1
, A
0
) = (0,1,0), and apply the write pulse during the Hidden ROM mode. To verify the protect circuit, apply high
voltage (V
ID
) to A
9
, specify (A
6
, A
1
, A
0
) = (0,1,0) and the sector address in the Hidden ROM area, and read.
When “1” appears to DQ
0
, the protect setting is completed. “0” will appear to DQ
0
if it is not protected. Please
apply write pulse again. The same command sequence could be used for the above method because other than
the Hidden ROM mode, it is the same as the sector group protect in the past. Please refer to “Function Explanation
Sector Group Protection
” for details of sector group protect setting
Other sector group will be effected if the address other than the Hidden ROM area is selected for the sector
group address, so please be careful. Once it is protected, protection can not be cancelled, so please pay closest
attention.
Write Operation Status
Detailed in Table 14 are all the status flags that can determine the status of the bank for the current mode
operation. The read operation from the bank where is not operate Embedded Algorithm returns a data of memory
cell. These bits offer a method for determining whether a Embedded Algorithm is completed properly. The
information on DQ
2
is address sensitive. This means that if an address from an erasing sector is consecutively
read, then the DQ
2
bit will toggle. However, DQ
2
will not toggle if an address from a non-erasing sector is
consecutively read. This allows the user to determine which sectors are erasing and which are not.
The status flag is not output from bank (non-busy bank) not executing Embedded Algorithm. For example, there
is bank (busy bank) which is now executing Embedded Algorithm. When the read sequence is [1] <busy bank>,
[2] <non-busy bank>, [3] <busy bank>, the DQ
6
is toggling in the case of [1] and [3]. In case of [2], the data of
memory cell is outputted. In the erase-suspend read mode with the same read sequence, DQ
6
will not be toggled
in the [1] and [3].
In the erase suspend read mode, DQ
2
is toggled in the [1] and [3]. In case of [2], the data of memory cell is
outputted.
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