參數(shù)資料
型號: MBM29DL324TE90TR
廠商: FUJITSU LTD
元件分類: DRAM
英文描述: 32M (4M x 8/2M x 16) BIT Dual Operation
中文描述: 2M X 16 FLASH 3V PROM, 90 ns, PDSO48
封裝: PLASTIC, REVERSE, TSOP1-48
文件頁數(shù): 51/80頁
文件大?。?/td> 1588K
代理商: MBM29DL324TE90TR
MBM29DL32XTE/BE
-80/90/12
51
2.
AC Characteristics
Read Only Operations Characteristics
Note: Test Conditions:
Output Load:1 TTL gate and 30 pF (MBM29DL32XTE/BE-80)
1 TTL gate and 100 pF (MBM29DL32XTE/BE-90/12)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output:1.5 V
Parameter
symbols
Description
Test setup
80
(Note)
90
(Note)
12
(Note)
Unit
JEDEC
Standard
t
AVAV
t
RC
Read Cycle Time
Min.
80
90
120
ns
t
AVQV
t
ACC
Address to Output Delay
CE = V
IL
OE = V
IL
Max.
80
90
120
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE = V
IL
Max.
80
90
120
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max.
30
35
50
ns
t
EHQZ
t
DF
Chip Enable to Output High-Z
Max.
25
30
30
ns
t
GHQZ
t
DF
Output Enable to Output High-Z
Max.
25
30
30
ns
t
AXQX
t
OH
Output Hold Time from Addresses,
CE or OE, Whichever Occurs First
Min.
0
0
0
ns
t
READY
RESET Pin Low to Read Mode
Max.
20
20
20
μ
s
t
ELFL
t
ELFH
CE or BYTE Switching Low or High
Max.
5
5
5
ns
C
L
3.3 V
Diodes = IN3064
or Equivalent
2.7 k
Device
Under
Test
IN3064
or Equivalent
6.2 k
Figure 4 Test Conditions
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相關代理商/技術參數(shù)
參數(shù)描述
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