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參數(shù)資料
| 型號： | MBM29DL640E90 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| 中文描述： | 64米（8的MX 8 / 4的MX 16）位雙操作 |
| 文件頁數(shù)： | 35/71頁 |
| 文件大?。?/td> | 913K |
| 代理商： | MBM29DL640E90 |
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MBM29DL640E
80/90/12
35
DQ
5
Exceeded Timing Limits
DQ
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under
these conditions DQ
5
will produce “1”. This is a failure condition indicating that the program or erase cycle was
not successfully completed. Data Polling is only operating function of the device under this condition. The CE
circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and WE pins
will control the output disable functions as described in Tables 2 and 3.
The DQ
5
failure condition may also appear if a user tries to program a non-blank location without pre-erase. In
this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads valid data on DQ
7
bit and DQ
6
never stop toggling. Once the device has exceeded timing limits, the DQ
5
bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used.
If this occurs, reset device with the command sequence.
DQ
3
Sector Erase Timer
After completion of the initial sector erase command sequence, sector erase time-out begins. DQ
3
will remain
low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command
sequence.
If Data Polling or the Toggle Bit I indicates that a valid erase command has been written, DQ
3
may be used to
determine whether the sector erase timer window is still open. If DQ
3
is high (“1”) the internally controlled erase
cycle has begun. If DQ
3
is low (“0”) , the device will accept additional sector erase commands. To insure the
command has been accepted, the system software should check the status of DQ
3
prior to and following each
subsequent Sector Erase command. If DQ
3
were high on the second status check, the command may not have
been accepted.
See Table 12 : Hardware Sequence Flags.
DQ
2
Toggle Bit II
This toggle bit II, along with DQ
6
, can be used to determine whether the device is in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
2
to toggle during the Embedded Erase Algorithm. If the
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
2
to toggle. When the device is in the erase-suspended-program mode, successive reads from
the non-erase
suspended sector will indicate a logic “1” at the DQ
2
bit.
DQ
6
is different from DQ
2
in that DQ
6
toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ
7
, is summarized
as follows :
For example, DQ
2
and DQ
6
can be used together to determine if the erase-suspend-read mode is in progress.
(DQ
2
toggles while DQ
6
does not.) See also Table 13 and Figure 12.
Furthermore DQ
2
can also be used to determine which sector is being erased. At the erase mode, DQ
2
toggles
if this bit is read from an erasing sector.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
Reading Toggle Bits DQ
6
/DQ
2
Whenever the system initially begins reading toggle bit status, it must read DQ
7
to DQ
0
at least twice in a row
to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ
7
to DQ
0
on the following read cycle.
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| MBM29DL640E90PBT | 64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL640E90TN | 64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL640E90TR | 64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL64DF | FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29DL640E90PBT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL640E90TN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL640E90TN-LE1 | 制造商:Spansion 功能描述: |
| MBM29DL640E90TR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL64DF | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT |
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