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參數(shù)資料
| 型號： | MBM29F002BC-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 2M (256K X 8) BIT |
| 中文描述： | 200萬（256K × 8）位 |
| 文件頁數(shù)： | 17/46頁 |
| 文件大?。?/td> | 461K |
| 代理商： | MBM29F002BC-70 |
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17
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
Just prior to the completion of Embedded Algorithm operation DQ
7
may change asynchronously while the output
enable (OE) is asserted low. This means that the device is driving status information on DQ
7
at one instant of
time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ
7
output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations
and DQ
7
has a valid data, the data outputs on DQ
0
to DQ
6
may be still invalid. The valid data on DQ
0
to DQ
7
will
be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, Erase Suspend, erase-suspend-program mode, or sector erase time-out. (See Table 7.)
See Figure 9 for the Data Polling timing specifications and diagrams.
DQ
6
Toggle Bit I
The MBM29F002TC/BC also features the “Toggle Bit I” as a method to indicate to the host system that the
embedded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device at any addresswill result in DQ
6
toggling between one and zero. Once the Embedded Program or
Erase Algorithm cycle is completed, DQ
6
will stop toggling and valid data will be read on the nextsuccessive
attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four
write pulse sequence. For chip erase, and sector erase the Toggle Bit I is valid after the rising edge of the sixth
WE pulse in the six write pulse sequence. For Sector Erase, the Toggle Bit I is valid after the last rising edge of
the sector erase WE pulse. The Toggle Bit I is active during the sector erase time out.
In programming, if the sector being written to is protected, the Toggle Bit I will toggle for about 2
μ
s and then
stop toggling without the data having changed. In erase, the device will erase all the selected sectors except for
the ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about
100
μ
s and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ
6
to toggle. In addition, an Erase Suspend/Resume command will
cause DQ
6
to toggle.
See Figure 10 for the Toggle Bit I timing specifications and diagrams.
DQ
5
Exceeded Timing Limits
DQ
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ
5
will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling DQ
7
, DQ
6
is the only operating function of the device under
this condition. The CE circuit will partially power down the device under these conditions (to approximately 2
mA). The OE and WE pins will control the output disable functions as described in Table 2.
The DQ
5
failure condition may also appear if a user tries to program a 1 to a location that is previously programmed
to 0. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the
system never reads a valid data on DQ
7
bit and DQ
6
never stops toggling. Once the device has exceeded timing
limits, the DQ
5
bit will indicate a “1.” Please note that this is not a device failure condition since the device was
incorrectly used. If this occurs, reset the device.
相關PDF資料 |
PDF描述 |
|---|---|
| MBM29F002BC-90 | 2M (256K X 8) BIT |
| MBM29F002TC-55 | 2M (256K X 8) BIT |
| MBM29F002TC | 2M (256K X 8) BIT |
| MBM29F002TC-90 | 2M (256K X 8) BIT |
| MBM29F002B | 2M (256K ×8) Bit Flash Memory( 單5V 電源電壓256K ×8位閃速存儲器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29F002BC-90 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8) BIT |
| MBM29F002T-90PD# | 制造商:FUJITSU 功能描述: |
| MBM29F002TC | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8) BIT |
| MBM29F002TC-55 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8) BIT |
| MBM29F002TC-70 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8) BIT |
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