![](http://datasheet.mmic.net.cn/330000/MBM29F160BE-55PFTN_datasheet_16438796/MBM29F160BE-55PFTN_21.png)
MBM29F160TE
-55/-70/-90
/MBM29F160BE
-55/-70/-90
21
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in Tables 2 and 3.
The DQ
5
failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
7
and DQ
6
never stops toggling. Once the device has exceeded timing limits, the DQ
5
bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used.
If this occurs, reset the device with command sequence.
DQ
3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
3
will
remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ
3
may
be used to determine if the sector erase timer window is still open. If DQ
3
is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ
3
is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ
3
prior to and following each subsequent sector erase command. If DQ
3
is high on the
second status check, the command may not have been accepted.
See Table 9: Hardware Sequence Flags.
DQ
2
Toggle Bit II
This Toggle Bit II, along with DQ
6
, can be used to determine whether the device is in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
2
to toggle during the Embedded Erase Algorithm. If the
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
2
to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at DQ
2
.
DQ
6
is different from DQ
2
in that DQ
6
toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress.
Notes: 1. Performing successive read operations from any address will cause DQ
6
to toggle.
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic “1” at the DQ
2
bit. However, successive reads from the erase-suspended sector will cause DQ
2
to
toggle.
For example, DQ
2
and DQ
6
can be used together to determine if the erase-suspend-read mode is in progress.
(DQ
2
toggles while DQ
6
does not.) See also Table 10 and Figure 18.
Table 10 Toggle Bit Status
Mode
DQ
7
DQ
6
DQ
2
Program
DQ
7
Toggle
1
Erase
0
Toggle
Toggle
Erase Suspend Read
(Erase Suspended Sector)
(Note 1)
1
1
Toggle
Erase-Suspend Program
DQ
7
Toggle (Note 1)
1 (Note 2)