參數(shù)資料
型號(hào)： MBM29F200BC-90PFTN
廠商： FUJITSU LTD
元件分類： DRAM
英文描述： Replaced by TPS2042B : 0.7A, 2.7-5.5V Dual (1In/2Out) Hi-Side MOSFET, Fault Report, Act-Low Enable 8-SOIC 0 to 85
中文描述： 128K X 16 FLASH 5V PROM, 90 ns, PDSO48
封裝： PLASTIC, TSOP1-48
文件頁(yè)數(shù)： 15/48頁(yè)
文件大?。?/td> 508K
代理商： MBM29F200BC-90PFTN
15
MBM29F200TC
-55/-70/-90
/MBM29F200BC
-55/-70/-90
The device will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A
9
to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read
cycle from address XX01H for
×
16 (XX02H for
×
8) returns the device code (MBM29F200TC = 51H and
MBM29F200BC = 57H for
×
8 mode; MBM29F200TC = 2251H and MBM29F200BC = 2257H for
×
16 mode).
(See Tables 4.1 and 4.2.)
All manufacturer and device codes will exhibit odd parity with DQ
7
defined as the parity bit.
Scanning the sector addresses ( A
16
, A
15
, A
14
, A
13
, and A
12
) while (A
6
, A
1
, A
0
) = (0, 1, 0) will produce a logical “1”
at device output DQ
0
for a protected sector. The programming verification should be perform margin mode on
the protected sector (See Tables 2 and 3).
To terminate the operation, it is necessary to write the read/reset command sequence into the register and also
to write the autoselect command during the operation, execute it after writing read/reset command sequence.
Byte/Word Programming
The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.
There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the
rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins
programming. Upon executing the Embedded Program
TM
Algorithm command sequence the system is not
required to provide further controls or timings. The device will automatically provide adequate internally generated
program pulses and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ
7
is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched (see Table 8, Hardware
Sequence Flags) Therefore, the devices require that a valid address to the devices be supplied by the system
at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Figure 19 illustrates the Embedded Programming Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
相關(guān)PDF資料
PDF描述
MBM29F200BC-90PFTR Replaced by TPS2042B : 0.7A, 2.7-5.5V Dual (1In/2Out) Hi-Side MOSFET, Fault Report, Act-Low Enable 8-SOIC 0 to 85
MBM29F200TC Replaced by TPS2042B : 0.7A, 2.7-5.5V Dual (1In/2Out) Hi-Side MOSFET, Fault Report, Act-Low Enable 8-SOIC 0 to 85
MBM29F200TC-55 Dual, Current-Limited, Power-Distribution Switches 8-SOIC -40 to 85
MBM29F200TC-55PF Dual, Current-Limited, Power-Distribution Switches 8-SOIC -40 to 85
MBM29F200TC-55PFTN Dual, Current-Limited, Power-Distribution Switches 8-MSOP-PowerPAD -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MBM29F200BC-90PFTN-SFL(E1) 制造商:Spansion 功能描述:
MBM29F200BC-90PFTR 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8/128K X 16) BIT
MBM29F200TC 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8/128K X 16) BIT
MBM29F200TC-55 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8/128K X 16) BIT
MBM29F200TC-55PF 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8/128K X 16) BIT
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