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參數(shù)資料
| 型號： | MBM29LV002B-10 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 2M (256K ×8) Bit Flash Memory(2M (256K ×8)位 單5V 電源電壓閃速存儲器) |
| 中文描述： | 200萬（256K × 8）位閃存（200萬（256K × 8）位單5V的電源電壓閃速存儲器） |
| 文件頁數(shù)： | 19/45頁 |
| 文件大?。?/td> | 406K |
| 代理商： | MBM29LV002B-10 |
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19
MBM29LV002T
-10/-12
/MBM29LV002B
-10/-12
RESET
Hardware Reset
The MBM29LV002T/002B devices may be reset by driving the RESET pin to V
IL
. The RESET pin has a pulse
requirement and has to be kept low (V
IL
) for at least 500 ns in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20
μ
s after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices requires an additional 50 ns before it will allow read access. When the RESET pin is low, the device will
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See Figure 10 for the timing
diagram. Refer to Temporary Sector Unprotection for additional functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)
cannot be used.
Data Protection
The MBM29LV002T/002B are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The devices also incorporates several features to prevent inadvertent write cycles resulting form V
CC
power-up
and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than 2.5 V (typically 2.4 V). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the Read mode. Subsequent writes will be ignored
until the V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically
correct to prevent unintentional writes when V
CC
is above 2.5 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
, or WE = V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29LV002B-12 | 2M (256K ×8) Bit Flash Memory(2M (256K ×8)位 單5V 電源電壓閃速存儲器) |
| MBM29LV002T-10 | 2M (256K ×8) Bit Flash Memory(2M (256K ×8)位 單5V 電源電壓閃速存儲器) |
| MBM29LV004BC | 4M (512K X 8) BIT |
| MBM29LV004TC | 4M (512K X 8) BIT |
| MBM29LV004TC-70PNS | 4M (512K X 8) BIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29LV002BC | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K x 8) BIT |
| MBM29LV002BC-12 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K x 8) BIT |
| MBM29LV002BC-12PNS | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K x 8) BIT |
| MBM29LV002BC-12PTN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K x 8) BIT |
| MBM29LV002BC-12PTR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K x 8) BIT |
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