參數(shù)資料
型號(hào)： MBM29LV080A-90
廠商： Fujitsu Limited
英文描述： 8M (1M x 8) BIT
中文描述： 8米（1米× 8）位
文件頁(yè)數(shù)： 20/49頁(yè)
文件大?。?/td> 400K
代理商： MBM29LV080A-90
MBM29LV080A
-70/-90/-12
20
Table 8 Toggle Bit Status
Notes: 1. Performing successive read operations from any address will cause DQ
6
to toggle.
2. Reading the address being programmed while in the erase-suspend program mode will indicate logic “1”
at the DQ
2
bit. However, successive reads from the erase-suspended sector will cause DQ
2
to toggle.
RY/BY
Ready/Busy Pin
The MBM29LV080A provides a RY/BY open-drain output pin as a way to indicate to the host system that the
Embedded
Algorithms are either in progress or has been completed. If the output is low, the device is busy with
either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase
operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands
with the exception of the Erase Suspend command. If the MBM29LV080A is placed in an Erase Suspend mode,
the RY/BY output will be high, by means of connecting with a pull up resistor to V
CC
.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. See Figure 11 and 12 for a detailed timing diagram. The RY/BY pin is
pulled high in stadby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V
CC
.
RESET
Hardware Reset Pin
The MBM29LV080A device may be reset by driving the RESET pin to V
IL
. The RESET pin has a pulse requirement
and has to be kept low (V
IL
) for at least 500 ns in order to properly reset the internal state machine. Any operation
in the process of being executed will be terminated and the internal state machine will be reset to the read mode
t
READY
after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices requires an
additional t
RH
before it will allow read access. When the RESET pin is low, the device will be in the standby mode
for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a
program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY
output signal should be ignored during the RESET pulse. See Figure 12 for the timing diagram. Refer to Tem-
porary Sector Unprotection for additional functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)
cannot be used.
Mode
DQ
7
DQ
6
DQ
2
Program
DQ
7
Toggle
1
Erase
0
Toggle
Toggle
Erase-Suspend Read
(Erase-Suspended Sector)
(Note 1)
1
1
Toggle
Erase-Suspend Program
DQ
7
Toggle (Note 1)
1 (Note 2)
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