- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377951 > MBM29LV320TE90TR (FUJITSU LTD) 32 M (4 M X 8/2 M X 16) BIT PDF資料下載
參數(shù)資料
| 型號： | MBM29LV320TE90TR |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | 32 M (4 M X 8/2 M X 16) BIT |
| 中文描述： | 2M X 16 FLASH 3V PROM, 90 ns, PDSO48 |
| 封裝： | PLASTIC, REVERSE, TSOP1-48 |
| 文件頁數(shù)： | 32/64頁 |
| 文件大?。?/td> | 877K |
| 代理商： | MBM29LV320TE90TR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁當前第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
MBM29LV320TE/BE
80/90/10
32
WE pins will control the output disable functions as described in “MBM29LV320TE/BE User Bus Operations
Tables (BYTE = V
IH
and BYTE = V
IL
)” (
I
DEVICE BUS OPERATIONS).
The DQ
5
failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the device locks out and never complete the Embedded Algorithm operation. Hence, the system never
read valid data on DQ
7
bit and DQ
6
never stop toggling. Once the device has exceeded timing limits, the DQ
5
bit will indicate a “1.” Please note that this is not a device failure condition since device was incorrectly used. If
this occurs, reset device with command sequence.
16. DQ
3
Sector Erase Timer
After completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
3
will
remain low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or Toggle Bit I indicates device has been written with a valid erase command, DQ
3
may be used
to determine if the sector erase timer window is still open. If DQ
3
is high (“1”) the internally controlled erase cycle
has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is
completed as indicated by Data Polling or Toggle Bit I. If DQ
3
is low (“0”) , the device will accept additional sector
erase commands. To insure the command has been accepted, the system software should check the status of
DQ
3
prior to and following each subsequent Sector Erase command. If DQ
3
were high on the second status
check, the command may not have been accepted.
See “Hardware Sequence Flags Table”.
17. DQ
2
Toggle Bit II
This toggle bit II, along with DQ
6
, can be used to determine whether the device is in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
2
to toggle during the Embedded Erase Algorithm. If the
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ
2
to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address
of the non-erase suspended sector will indicate a logic “1” at the DQ
2
bit.
DQ
6
is different from DQ
2
in that DQ
6
toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ
7
, is summarized
as follows :
For example, DQ
2
and DQ
6
can be used together to determine if the erase-suspend-read mode is in progress.
(DQ
2
toggles while DQ
6
does not.) See also “Toggle Bit Status Table” and “8. DQ
2
vs DQ
6
” in
I
TIMING DIAGRAM.
Furthermore, DQ
2
can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ
2
toggles if this bit is read from an erasing sector.
18. Reading Toggle Bits DQ
6
/DQ
2
Whenever the system initially begins reading toggle bit status, it must read DQ
7
to DQ
0
at least twice in a row to
determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, this indicates that the device has completed the program or erase operation.
The system can read array data on DQ
7
to DQ
0
on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ
5
is high (see “15. DQ
5
”) . If it is the system should then determine
again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ
5
went high.
If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If
it is still toggling, the device did not complete the operation successfully, and the system must write the reset
command to return to reading array data.
相關PDF資料 |
PDF描述 |
|---|---|
| MBM29LV320TE80 | 32 M (4 M X 8/2 M X 16) BIT |
| MBM29LV320TE80PBT | 32 M (4 M X 8/2 M X 16) BIT |
| MBM29LV320TE80TN | 32 M (4 M X 8/2 M X 16) BIT |
| MBM29LV320TE80TR | 32 M (4 M X 8/2 M X 16) BIT |
| MBM29LV320BE90TR | 32 M (4 M X 8/2 M X 16) BIT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29LV400BC | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8/256K X 16) BIT |
| MBM29LV400BC-12 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8/256K X 16) BIT |
| MBM29LV400BC-12PBT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8/256K X 16) BIT |
| MBM29LV400BC-12PCV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8/256K X 16) BIT |
| MBM29LV400BC-12PF | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8/256K X 16) BIT |
發(fā)布緊急采購，3分鐘左右您將得到回復。