參數(shù)資料
型號(hào): MBM29LV400TC-90PF
廠商: FUJITSU LTD
元件分類: DRAM
英文描述: 4M (512K X 8/256K X 16) BIT
中文描述: 256K X 16 FLASH 3V PROM, 90 ns, PDSO44
封裝: PLASTIC, SOP-44
文件頁(yè)數(shù): 27/58頁(yè)
文件大?。?/td> 584K
代理商: MBM29LV400TC-90PF
27
MBM29LV400TC
-70/-90/-12
/MBM29LV400BC
-70/-90/-12
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than 2.3 V (typically 2.4 V). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when V
CC
is above 2.3 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
, or WE = V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the devices with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MBM29LV400TC-90PFTN 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8/256K X 16) BIT
MBM29LV400TC-90PFTN-S# 制造商:FUJITSU 功能描述:
MBM29LV400TC-90PFTR 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8/256K X 16) BIT
MBM29LV400TC-90PW 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 4M (512K X 8/256K X 16) BIT
MBM29LV650UE 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64M (4M x 16) BIT