- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377953 > MBM29PDS322TE11 (Fujitsu Limited) 32M (2M x 16) BIT Page Dual Operation PDF資料下載
參數(shù)資料
| 型號： | MBM29PDS322TE11 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 32M (2M x 16) BIT Page Dual Operation |
| 中文描述： | 32M的（2米× 16）位頁雙操作 |
| 文件頁數(shù)： | 30/66頁 |
| 文件大小： | 694K |
| 代理商： | MBM29PDS322TE11 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
MBM29PDS322TE/BE
10/11
30
DQ
7
Data Polling
The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in
progress or completed. During the Embedded Program Algorithm an attempt to read device will produce a
complement of data last written to DQ
7
. Upon completion of the Embedded Program Algorithm, an attempt to
read device will produce true data last written to DQ
7
. During the Embedded Erase Algorithm, an attempt to read
device will produce a “0” at the DQ
7
output. Upon completion of the Embedded Erase Algorithm an attempt to
read device will produce a “1” on DQ
7
. The flowchart for Data Polling (DQ
7
) is shown in Figure 23.
For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse
sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address of sectors being erased, not protected
sectors. Otherwise, the status may be invalid.
If a program address falls within a protected sector, Data Polling on DQ
7
is active for approximately 1
μ
s, then
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on DQ
7
is active for approximately 400
μ
s, then the bank returns to read mode.
Once the Embedded Algorithm operation is close to completion, the device data pins (DQ
7
) may change asyn-
chronously while the output enable (OE) is asserted low. This means that device is driving status information
on DQ
7
at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the
system samples the DQ
7
output, it may read the status or valid data. Even if device has completed the Embedded
Algorithm operation and DQ
7
has a valid data, data outputs on DQ
0
to DQ
6
may be still invalid. The valid data
on DQ
0
to DQ
7
will be read on the successive read attempts.
The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See Table 9.)
See Figure 10 for the Data Polling timing specifications and diagrams.
DQ
6
Toggle Bit I
The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the
device will results in DQ
6
toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle
is completed, DQ
6
will stop toggling and valid data will be read on the next successive attempts. During pro-
gramming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written is protected, the toggle bit will toggle for about 1
μ
s and then stop
toggling with data unchanged. In erase, device will erase all selected sectors except for ones that are protected.
If all selected sectors are protected, the chip will toggle the toggle bit for about 400 μs and then drop back into
read mode, having data unchanged.
Either CE or OE toggling will cause DQ
6
to toggle. In addition, an Erase Suspend/Resume command will cause
DQ
6
to toggle.
The system can use DQ
6
to determine whether a sector is actively erased or is erase-suspended. When a bank
is actively erased (that is, the Embedded Erase Algorithm is in progress), DQ
6
toggles. When a bank enters the
Erase Suspend mode, DQ
6
stops toggling. Successive read cycles during erase-suspend-program cause DQ
6
to toggle.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29PDS322TE11PBT | 32M (2M x 16) BIT Page Dual Operation |
| MBM29PDS322BE10 | 32M (2M x 16) BIT Page Dual Operation |
| MBM29PDS322BE10PBT | NEOZED TYPE,400V.10A |
| MBM29PDS322BE11 | 32M (2M x 16) BIT Page Dual Operation |
| MBM29PDS322BE11PBT | 32M (2M x 16) BIT Page Dual Operation |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM30000 | 功能描述:BRACKET SIDE MOUNT RoHS:是 類別:工業(yè)控制，儀表 >> 配件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:Aero-Motive® 130117 附件類型:拖車帶 適用于相關(guān)產(chǎn)品:標(biāo)準(zhǔn)盒式跟蹤系統(tǒng) 其它名稱:WM6183 |
| MBM30035001 | 制造商:LG Corporation 功能描述:Card,Technical |
| MBM30035015 | 制造商:LG Corporation 功能描述:Card,Technical |
| MBM300A6 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:IGBT MODULE RANGE WITH SOFT AND FAST (SFD) FREE-WHEELING DIODES |
| MBM300GR12A | 制造商:n/a 功能描述:IGBT Module |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。