- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377953 > MBM29PL160BD-90PF (FUJITSU LTD) 16M (2M x 8/1M x 16) BIT PDF資料下載
參數(shù)資料
| 型號(hào)： | MBM29PL160BD-90PF |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | 16M (2M x 8/1M x 16) BIT |
| 中文描述： | 1M X 16 FLASH 3V PROM, 90 ns, PDSO44 |
| 封裝： | PLASTIC, SOP-44 |
| 文件頁數(shù)： | 16/51頁 |
| 文件大?。?/td> | 591K |
| 代理商： | MBM29PL160BD-90PF |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁
16
MBM29PL160TD
-75/-90
/MBM29PL160BD
-75/-90
MBM29PL160BD = 45H for
×
8 mode; MBM29PL160TD = 2227H and MBM29PL160BD = 2245H for
×
16 mode).
(See Tables 4.1 and 4.2.)
All manufactures and device codes will exhibit odd parity with DQ
7
defined as the parity bit.
The sector state (protection or unprotection) will be indicated by address XX02H for
×
16 (XX04H for
×
8).
Scanning the sector addresses (A
19
, A
18
, A
17
, A
16
, A
15
, A
14
, A
13
, and A
12
) while (A
6
, A
1
, A
0
) = (0, 1, 0) will produce
a logical “1” at device output DQ
0
for a protected sector. The programming verification should be perform margin
mode verification on the protected sector. (See Tables 2 and 3.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and,
also to write the Autoselect command during the operation, by executing it after writing the Read/Reset command
sequence.
Word/Byte Programming
The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.
There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the
rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens
first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system
is not required to provide further controls or timings. The device will automatically provide adequate internally
generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.)
The automatic programming operation is completed when the data on DQ
7
is equivalent to data written to this
bit at which time the device return to the read mode and addresses are no longer latched. (See Table 9, Hardware
Sequence Flags.) Therefore, the device requires that a valid address be supplied by the system at this time.
Hence, Data Polling must be performed at the memory location which is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occures during the
programming operation, it is impossible to guarantee whether the data being written is correct or not.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Figure 16 illustrates the Embedded Program
TM
Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. (Preprogram Function.) The system is not required to provide any controls
or timings during these operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ
7
is “1” (See Write Operation Status section.) at which time the device returns to read mode.
(See Figure 8.)
Figure 17 illustrates the Embedded Erase
TM
Algorithm using typical command strings and bus operations.
Sector Erase
Sector erase is a six-bus cycle operation. There are two “unlock” write cycles, followed by writing the “set-up”
command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address
(any address location within the desired sector) is latched on the falling edge of WE, while the command (Data
= 30H) is latched on the rising edge of WE. After a time-out of 50
μ
s from the rising edge of the last sector erase
command, the sector erase operation will begin.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29PL160BD-90PFTN | 16M (2M x 8/1M x 16) BIT |
| MBM29PL160BD-90PFTR | 16M (2M x 8/1M x 16) BIT |
| MBM29PL160BD | 16M (2M x 8/1M x 16) BIT |
| MBM29PL160TD-75 | 122 x 32 pixel format, LED Backlight available |
| MBM29PL160TD-75PF | 122 x 32 pixel format, LED Backlight available |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM30000 | 功能描述:BRACKET SIDE MOUNT RoHS:是 類別:工業(yè)控制，儀表 >> 配件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:Aero-Motive® 130117 附件類型:拖車帶 適用于相關(guān)產(chǎn)品:標(biāo)準(zhǔn)盒式跟蹤系統(tǒng) 其它名稱:WM6183 |
| MBM30035001 | 制造商:LG Corporation 功能描述:Card,Technical |
| MBM30035015 | 制造商:LG Corporation 功能描述:Card,Technical |
| MBM300A6 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:IGBT MODULE RANGE WITH SOFT AND FAST (SFD) FREE-WHEELING DIODES |
| MBM300GR12A | 制造商:n/a 功能描述:IGBT Module |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。