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參數(shù)資料
| 型號： | MBM29PL160BD-90PFTN |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | 16M (2M x 8/1M x 16) BIT |
| 中文描述： | 1M X 16 FLASH 3V PROM, 90 ns, PDSO48 |
| 封裝： | PLASTIC, TSOP1-48 |
| 文件頁數(shù)： | 22/51頁 |
| 文件大?。?/td> | 591K |
| 代理商： | MBM29PL160BD-90PFTN |
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22
MBM29PL160TD
-75/-90
/MBM29PL160BD
-75/-90
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than 2.3 V (typically 2.4 V). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when V
CC
is above 2.3 V.
If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) will need to be
erased again prior to programming.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not change the command registers.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
, or WE = V
IH
. To initiate a write, CE and WE must
be a logical zero while OE is a logical one.
Power-up Write Inhibit
Power-up of the devices with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to read mode on power-up.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29PL160BD-90PFTR | 16M (2M x 8/1M x 16) BIT |
| MBM29PL160BD | 16M (2M x 8/1M x 16) BIT |
| MBM29PL160TD-75 | 122 x 32 pixel format, LED Backlight available |
| MBM29PL160TD-75PF | 122 x 32 pixel format, LED Backlight available |
| MBM29PL160TD-75PFTN | 122 x 32 pixel format, LED Backlight available |
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