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參數(shù)資料
| 型號： | MBM29PL160TD |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16M (2M x 8/1M x 16) BIT |
| 中文描述： | 16米（2米x 8/1M × 16）位 |
| 文件頁數(shù)： | 20/51頁 |
| 文件大?。?/td> | 591K |
| 代理商： | MBM29PL160TD |
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20
MBM29PL160TD
-75/-90
/MBM29PL160BD
-75/-90
DQ
6
Toggle Bit I
The MBM29PL160TD/BD also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device will result in DQ
6
toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ
6
will stop toggling and valid data can be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six-
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 1
μ
s and then stop
toggling without the data having changed. In erase, the device will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about
100
μ
s and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ
6
to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ
6
to toggle.
See Figure 10 and Figure 19 for the Toggle Bit I timing specifications and diagrams.
DQ
5
Exceeded Timing Limits
DQ
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ
5
will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the device under this
condition. The CE circuit will partially power down the device under these conditions. The OE and WE pins will
control the output disable functions as described in Tables 2 and 3.
The DQ
5
failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
7
and DQ
6
never stops toggling. Once the device has exceeded timing limits, the DQ
5
bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used.
If this occurs, reset the device with command sequence.
DQ
3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
3
will
remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ
3
may
be used to determine if the sector erase timer window is still open. If DQ
3
is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ
3
is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ
3
prior to and following each subsequent sector erase command. If DQ
3
is high on the
second status check, the command may not have been accepted.
See Table 9: Hardware Sequence Flags.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29PL160BD-75 | 16M (2M x 8/1M x 16) BIT |
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| MBM29PL160BD-75PFTR | 16M (2M x 8/1M x 16) BIT |
| MBM29PL160BD-90 | 16M (2M x 8/1M x 16) BIT |
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