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參數資料
| 型號： | MC-80C32E-30/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 30 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | SIDE BRAZED, DIP-40 |
| 文件頁數： | 19/20頁 |
| 文件大?。?/td> | 239K |
| 代理商： | MC-80C32E-30/883 |
8
80C32E
Rev. K – 21-Aug-01
Power-Down Mode
To save maximum power, a power-down mode can be invoked by software.
In power-down mode, the oscillator is stopped and the instruction that invoked power-
down mode is the last instruction executed. The internal RAM and SFRs retain their
value until the power-down mode is terminated. V
CC can be lowered to save further
power. Either a hardware reset or an external interrupt can cause an exit from power-
down. To properly terminate power-down, the reset or external interrupt should not be
executed before V
CC is restored to its normal operating level and must be held active
long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that,
interrupt must be enabled and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as
detailed in Figure 1. When both interrupts are enabled, the oscillator restarts as soon as
one of the two inputs is held low and power down exit will be completed when the first
input will be released. In this case the higher priority interrupt service routine is exe-
cuted.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the
one following the instruction that put 80C32E into power-down mode.
Figure 1. Power-Down Exit Waveform
Exit from power-down by reset redefines all the SFRs, exit from power-down by external
interrupt does no affect the SFRs.
Exit from power-down by either reset or external interrupt does not affect the internal
RAM content.
Note:
If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence
is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and
idle mode is not entered.
Table 2. The state of ports during idle and power-down modes
INT1
INT0
XTAL1
Power-down phase
Oscillator restart phase
Active phase
Mode
Program
Memory
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle
External
1
Floating
Port Data
Address
Port Data
Power Down
External
0
Floating
Port Data
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