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參數(shù)資料
| 型號(hào)： | MC100EP195BMNR4G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 100EP |
| 標(biāo)片/步級(jí)數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 2.5ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 2.2ns ~ 12.2ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | MC100EP195BMNR4GOSCT |
MC100EP195B
http://onsemi.com
10
Table 10. AC CHARACTERISTICS VCC = 0 V; VEE = 3.0 V to 3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 14)
Symbol
Characteristic
40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Frequency
1.2
GHz
VoutPP
Output Voltage Amplitude
610
820
610
820
610
820
mV
tPLH
tPHL
Propagation Delay
IN to Q; D(010) = 0, SETMIN
IN to Q; D(010) = 1023, SETMAX
EN to Q; D(010) = 0
D0 to CASCADE
2000
10900
1990
375
2400
12400
2500
475
2800
13900
2990
575
2150
11500
2130
400
2500
13000
2600
500
2950
14500
3130
600
2250
12250
2380
425
2700
13750
2800
525
3050
15250
3380
625
ps
tRANGE
Programmable Range
tPD (max) tPD (min)
8950
9950
10950
9450
10450 11450 10110 11100 12110
ps
Dt
Step Delay (Note 15)
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
10
16
32
65
155
310
620
1200
2500
4900
11
18
33
72
165
325
650
1300
2600
5200
15
26
46
92
195
370
720
1400
2800
5500
ps
NLIN
NonLinearity (Note 21)
0 to 511 Decimal Values for
D[9:0] Range
512 to 1024 Decimal Values for
D[9:0] Range
1 to 1023 Decimal Values for
D[9:0] Range
$7.0
$11
$7.0
$11
$18
ps
tSKEW
Duty Cycle Skew (Note 16)
|tPHLtPLH|
25
90
25
90
25
90
ps
ts
Setup Time
D to LEN
D to IN (Note 17)
EN to IN (Note 18)
200
500
300
40
550
100
200
500
300
40
590
100
200
500
300
40
650
120
ps
th
Hold Time
LEN to D
IN to EN (Note 19)
200
400
50
320
200
400
40
350
200
400
30
400
ps
tR
Release Time
EN to IN (Note 20)
SET MAX to LEN
SET MIN to LEN
300
400
350
150
180
220
300
400
350
170
200
250
300
400
350
200
210
260
ps
tjitter
RMS Random Clock Jitter @ 1.2 GHz
IN to Q; D(0:10) = 0 or SETMIN
IN to Q; D(0:10) = 1023 or SETMAX
0.9
1.9
2.0
5.0
1.1
2.6
2.0
5.0
1.2
3.3
2.0
5.0
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
15.Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations
of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
16.Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
17.This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
18.This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater
than ±75 mV to that IN/IN transition.
19.This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output re-
sponse greater than ±75 mV to that IN/IN transition.
20.This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
21.Deviation from a linear delay (actual Min to Max) in the 1024 programmable steps.
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