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參數(shù)資料
| 型號(hào)： | MC100EP196FAG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 12/18頁 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | 100EP |
| 標(biāo)片/步級(jí)數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 2.36ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 2.36ns ~ 12.258ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-LQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | MC100EP196FAGOS |
MC100EP196
http://onsemi.com
3
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Default State
Description
23, 25, 26, 27,
29, 30, 31, 32,
1, 2
D[0:9]
LVCMOS, LVTTL,
ECL Input
LOW
Singleended Parallel Data Inputs [0:9]. Internal 75 kW to VEE.
(Note 1)
3
D[10]
LVCMOS, LVTTL,
ECL Input
LOW
Singleended CASCADE/CASCADE Control Input. Internal 75 kW
4
IN
ECL Input
LOW
Noninverted Differential Input. Internal 75 kW to VEE.
5
IN
ECL Input
HIGH
Inverted Differential Input. Internal 75 kW to VEE.
6
VBB
ECL Reference Voltage Output
7
VEF
Reference Voltage for ECL Mode Connection
8
VCF
LVCMOS, ECL, OR LVTTL Input Mode Select
9, 28
VEE
Negative Supply Voltage. All VEE Pins must be Externally Connec-
ted to Power Supply to Guarantee Proper Operation. (Note 2)
13, 18, 19, 22
VCC
Positive Supply Voltage. All VCC Pins must be externally Connec-
ted to Power Supply to Guarantee Proper Operation. (Note 2)
10
LEN
ECL Input
LOW
Singleended D pins LOAD / HOLD input. Internal 75 kW to VEE.
11
SETMIN
ECL Input
LOW
Singleended Minimum Delay Set Logic Input. Internal 75 kW to
12
SETMAX
ECL Input
LOW
Singleended Maximum Delay Set Logic Input. Internal 75 kW to
14
CASCADE
ECL Output
Inverted Differential Cascade Output for D[10] Input. Typically Ter-
minated with 50 W to VTT = VCC 2 V.
15
CASCADE
ECL Output
Noninverted Differential Cascade Output for D[10] Input. Typically
Terminated with 50 W to VTT = VCC 2 V.
16
EN
ECL Input
LOW
Singleended Output Enable Pin. Internal 75 kW to VEE.
17
FTUNE
Analog Input
Fine Tuning Input.
21
Q
ECL Output
Noninverted Differential Output. Typically Terminated with 50 W to
VTT = VCC 2 V.
20
Q
ECL Output
Inverted Differential Output. Typically Terminated with 50 W to
VTT = VCC 2 V.
1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs.
2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP196FAG | 制造商:ON Semiconductor 功能描述:Delay Line IC |
| MC100EP196FAR2 | 功能描述:延遲線/計(jì)時(shí)元素 3.3V/5V ECL RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP196FAR2G | 功能描述:延遲線/計(jì)時(shí)元素 3.3V/5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP210S | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5V1:5 Dual Differential LVDS Compatible Clock Driver |
| MC100EP210S_06 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5V 1:5 Dual Differential LVDS Compatible Clock Driver |
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