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參數(shù)資料
| 型號(hào)： | MC100EP196FAG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | 100EP |
| 標(biāo)片/步級(jí)數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 2.36ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 2.36ns ~ 12.258ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-LQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | MC100EP196FAGOS |
MC100EP196
http://onsemi.com
14
An expansion of the latch section of the block diagram is
pictured in Figure 7. Use of this diagram will simplify the
explanation of how the SETMIN and SETMAX circuitry
works in cascade. When D10 of chip #1 in Figure 5 is LOW,
this device’s cascade output will also be LOW while the
CASCADE output will be HIGH. In this condition, the
SETMIN pin of chip #2 will be asserted HIGH and thus all
of the latches of chip #2 will be reset and the device will be
set at its minimum delay.
Chip #1, on the other hand, will have both SETMIN and
SETMAX deasserted so that its delay will be controlled
entirely by the address bus A0A9. If the delay needed is
greater than can be achieved with 1023 gate delays
(1111111111 on the A0A9 address bus), D10 will be
asserted to signal the need to cascade the delay to the next
EP196 device. When D10 is asserted, the SETMIN pin of
chip #2 will be deasserted and the SETMAX pin asserted,
resulting in the device delay to be the maximum delay.
Table 12 shows the delay time of two EP196 chips in
cascade.
To expand this cascading scheme to more devices, one
simply needs to connect the D10 pin from the next chip to
the address bus and CASCADE outputs to the next chip in
the same manner as pictured in Figure 6. The only addition
to the logic is the increase of one line to the address bus for
cascade control of the second programmable delay chip.
Furthermore, to fully utilize EP196, the FTUNE pin can
be used for additional delay and for finer resolution than
10 ps. As shown in Figure 5, an analog voltage input from
DAC can adjust the FTUNE pin with an extra 60 ps of delay
for each chip.
SET
MIN
SET
MAX
TO SELECT MULTIPLEXERS
BIT 0
D0 Q0
LEN
Set Reset
Figure 7. Expansion of the Latch Section of the EP196 Block Diagram
BIT 1
D1 Q1
LEN
Set Reset
BIT 2
D2 Q2
LEN
Set Reset
BIT 3
D3 Q3
LEN
Set Reset
BIT 4
D4 Q4
LEN
Set Reset
BIT 5
D5 Q5
LEN
Set Reset
BIT 6
D6 Q6
LEN
Set Reset
BIT 7
D7 Q7
LEN
Set Reset
BIT 8
D8 Q8
LEN
Set Reset
BIT 9
D9 Q9
LEN
Set Reset
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP196FAG | 制造商:ON Semiconductor 功能描述:Delay Line IC |
| MC100EP196FAR2 | 功能描述:延遲線/計(jì)時(shí)元素 3.3V/5V ECL RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP196FAR2G | 功能描述:延遲線/計(jì)時(shí)元素 3.3V/5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP210S | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5V1:5 Dual Differential LVDS Compatible Clock Driver |
| MC100EP210S_06 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5V 1:5 Dual Differential LVDS Compatible Clock Driver |
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