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參數(shù)資料
| 型號： | MC100LVE111 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 3.3V ECL 1:9 Differential Clock Driver(3.3V ECL 1:9 差分時鐘驅(qū)動器) |
| 中文描述： | 3.3 ECL 1:9差分時鐘驅(qū)動器（3.3V ECL 1:9差分時鐘驅(qū)動器） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 129K |
| 代理商： | MC100LVE111 |
Semiconductor Components Industries, LLC, 2006
November, 2006
Rev. 7
1
Publication Order Number:
MC100LVE111/D
MC100LVE111
3.3VECL 1:9 Differential
Clock Driver
The MC100LVE111 is a low skew 1
to
9 differential driver,
designed with clock distribution in mind. The MC100LVE111’s
function and performance are similar to the popular MC100E111, with
the added feature of low voltage operation. It accepts one signal input,
which can be either differential or single
ended if the V
BB
output is
used. The signal is fanned out to 9 identical differential outputs.
The LVE111 is specifically designed, modeled and produced with
low skew as the key goal. Optimal design and layout serve to minimize
gate to gate skew within a device, and empirical modeling is used to
determine process control limits that ensure consistent t
pd
distributions from lot to lot. The net result is a dependable, guaranteed
low skew device.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50 , even if
only one side is being used. In most applications, all nine differential
pairs will be used and therefore terminated. In the case where fewer
than nine pairs are used, it is necessary to terminate at least the output
pairs on the same package side as the pair(s) being used on that side, in
order to maintain minimum skew. Failure to do this will result in small
degradations of propagation delay (on the order of 10
20 ps) of the
output(s) being used which, while not being catastrophic to most
designs, will mean a loss of skew margin.
The MC100LVE111, as with most other ECL devices, can be
operated from a positive V
CC
supply in PECL mode. This allows the
LVE111 to be used for high performance clock distribution in +3.3 V
systems. Designers can take advantage of the LVE111’s performance
to distribute low skew clocks across the backplane or the board. In a
PECL environment, series or Thevenin line terminations are typically
used as they require no additional power supplies. For systems
incorporating GTL, parallel termination offers the lowest power by
taking advantage of the 1.2 V supply as a terminating voltage. For
more information on using PECL, designers should refer to
Application Note AN1406/D.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single
ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
200 ps Part
to
Part Skew
50 ps Output
to
Output Skew
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
CC
= 3.0 V to 3.8 V with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V with V
EE
=
3.0 V to
3.8 V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or at V
EE
Pb
Free Packages are Available*
MARKING
DIAGRAM*
1 28
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb
Free Package
PLCC
28
FN SUFFIX
CASE 776
*For additional marking information, refer to
Application Note AND8002/D.
MC100LVE111G
AWLYYWW
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
*For additional information on our Pb
Free strategy
and soldering details, please download the
ON Semiconductor
Soldering
Techniques Reference Manual, SOLDERRM/D.
and
Mounting
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PDF描述 |
|---|---|
| MC100LVE210 | 3.3V ECL Dual 1:4, 1:5 Differential Fanout Buffer(3.3V ECL 雙1:4，1:5 差分輸出緩沖器) |
| MC100LVE222 | 3.3V ECL 1:15 Differential ÷1/÷2 Clock Driver(低壓1:15差分ECL/PECL時鐘驅(qū)動器) |
| MC100LVE310 | 3.3V ECL 2:8 Differential Fanout Buffer(3.3V ECL 2：8 差分輸出緩沖器) |
| MC100LVEP05 | 2.5V / 3.3V ECL 2-Input Differential AND/NAND |
| MC100LVEP05DTG | 2.5V / 3.3V ECL 2-Input Differential AND/NAND |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100LVE111FN | 功能描述:時鐘緩沖器 3.3V ECL 1:9 DIFF RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MC100LVE111FNG | 功能描述:時鐘緩沖器 3.3V ECL 1:9 DIFF Clock Driver RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MC100LVE111FNG | 制造商:ON Semiconductor 功能描述:CLOCK GENERATOR / DISTRIBUTOR LOGIC IC |
| MC100LVE111FNR2 | 功能描述:時鐘緩沖器 3.3V ECL 1:9 DIFF RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MC100LVE111FNR2G | 功能描述:時鐘緩沖器 3.3V ECL 1:9 DIFF Clock Driver RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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