MC10197
3–169
MOTOROLA
MECL Data
DL122 — Rev 6
ELECTRICAL CHARACTERISTICS
Pin
Under
Test
Test Limits
–30
°
C
+25
°
C
+85
°
C
Characteristic
Symbol
Min
Max
Min
Typ
Max
Min
Max
Unit
Power Supply Drain Current
IE
IinH
8
54
39
49
54
mAdc
Input Current
5
9
425
460
265
290
265
290
μ
Adc
IinL
VOH
VOL
VOHA
VOLA
5
0.5
0.5
0.3
μ
Adc
Output Voltage
Logic 1
2
–1.060
–0.890
–0.960
–0.810
–0.890
–0.700
Vdc
Output Voltage
Logic 0
2
–1.890
–1.675
–1.850
–1.650
–1.825
–1.615
Vdc
Threshold Voltage
Logic 1
2
–1.080
–0.980
–0.910
Vdc
Threshold Voltage
Logic 0
2
–1.655
–1.630
–1.595
Vdc
Switching Times
(50
Load)
ns
Propagation Delay
t5+2+
t9+2+
t2+
t2–
2
2
1.1
1.1
4.2
5.3
1.1
1.1
2.8
3.5
4.0
5.0
1.1
1.1
4.4
5.5
Rise Time
(20 to 80%)
2
1.1
4.7
1.1
2.5
4.5
1.1
5.0
Fall Time
(20 to 80%)
2
1.1
4.7
1.1
2.5
4.5
1.1
5.0
ELECTRICAL CHARACTERISTICS
(continued)
TEST VOLTAGE VALUES
(Volts)
@ Test Temperature
VIHmax
–0.890
VILmin
–1.890
VIHAmin
–1.205
VILAmax
–1.500
VEE
–5.2
–30
°
C
+25
°
C
–0.810
–1.850
–1.105
–1.475
–5.2
+85
°
C
–0.700
–1.825
–1.035
–1.440
–5.2
Pin
Under
Test
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(VCC)
Gnd
Characteristic
Symbol
VIHmax
VILmin
VIHAmin
VILAmax
VEE
8
Power Supply Drain Current
IE
IinH
8
1, 16
Input Current
5
9
5
9
8
8
1, 16
1, 16
IinL
VOH
VOL
VOHA
VOLA
5
5
8
1, 16
Output Voltage
Logic 1
2
5, 9
8
1, 16
Output Voltage
Logic 0
2
8
1, 16
Threshold Voltage
Logic 1
2
9
5
8
1, 16
Threshold Voltage
Logic 0
2
9
5
8
1, 16
Switching Times
(50
Load)
+1.11V
Pulse In
Pulse Out
–3.2 V
+2.0 V
Propagation Delay
t5+2+
t9+2+
t2+
t2–
2
2
9
5
5
9
2
2
8
8
1, 16
1, 16
Rise Time
(20 to 80%)
2
9
5
2
8
1, 16
Fall Time
(20 to 80%)
2
9
5
2
8
1, 16
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.