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參數(shù)資料
| 型號： | MC10319P |
| 廠商： | MOTOROLA INC |
| 元件分類： | ADC |
| 英文描述： | Hex Buffers/Drivers With Open-Collector High-Voltage Outputs 14-CDIP -55 to 125 |
| 中文描述： | 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 338K |
| 代理商： | MC10319P |
MC10319
DESIGN GUIDELINES
8
MOTOROLA ANALOG IC DEVICE DATA
Introduction
The MC10319 is a high speed, 8–bit, parallel (“flash”) type
analog–to–digital converter containing 256 comparators at
the front end. See Figure 17 for a block diagram. The
comparators are arranged such that one input of each is
referenced to evenly spaced voltages, derived from the
reference resistor ladder. The other input of the comparators
is connected to the input signal (Vin). Some of the
comparator
′
s differential outputs will be “true,” while other
comparators will have “not true” outputs, depending on their
relative position. Their outputs are then latched, and
converted to an 8–bit Grey code by the Differential Latch
Array. The Grey code ensures that any input errors due to
cross talk, feed–thru, or timing disparities result in glitches at
the output of only a few LSBs, rather than the more traditional
1/2 scale and 1/4 scale glitches.
The Grey code is then translated to an 8–bit binary code,
and the differential levels are translated to TTL levels before
being applied to the output latches. Enable inputs at this final
stage permit the TTL outputs (except overrange) to be put
into a high impedance (3–state) condition.
ANALOG SECTION
Signal Input
The signal voltage to be digitized (Vin) is applied
simultaneously to one input of each of the 256 comparators
through Pin 14. The other inputs of the comparators are
connected to 256 evenly spaced voltages derived from the
reference ladder. The output code depends on the relative
position of the input signal and the reference voltages. The
comparators have a bandwidth of
than sufficient for the allowable (Nyquist Theorem) input
frequency of 12.5 MHz.
The current into Pin 14 varies linearly from 0 (when
Vin = VRB) to
≈
60
μ
A (when Vin = VRT). If Vin is taken below
VRB or above VRT, the input current will remain at the value
corresponding to VRB and VRT respectively (see Figure 5).
However, Vin must be maintained within the absolute range of
±
2.5 V (with respect to ground) – otherwise excessive
currents will result at Pin 14, due to internal clamps.
The input capacitance at Pin 14 is typically 36 pF if
[VRT – VRB] is 2.0 V, and increases to 55 pF if [VRT – VRB]
is reduced to 1.0 V (see Figure 4). The capacitance is
constant as Vin varies from VRT down to
≈
0.1 V above VRB.
Taking Vin to VRB will show an increase in the capacitance of
≈
50%. If Vin is taken above VRT, or below VRB, the
capacitance will stay at the values corresponding to VRT
and VRB, respectively.
The source impedance of the signal voltage should be
maintained below 100
(at the frequencies of interest) in
order to avoid sampling errors.
50 MHz, which is more
Reference
The reference resistor ladder is composed of a string of
equal value resistors to provide 256 equally spaced voltages
for the comparators (see Figure 17 for the actual
configuration). The voltage difference between adjacent
comparators corresponds to 1 LSB of the input range. The
first comparator (closest to VRB) is referenced 1/2 LSB above
VRB, and 256th comparator (for the overrange) is referenced
1/2 LSB below VRT. The total resistance of the ladder is
nominally 130
,
±
20%, requiring 15.4 mA @ 2.0 V, and
7.7 mA @ 1.0 V. There is a nominal warm–up change of
≈
+9.0% in the ladder resistance due to the +0.29%/
°
C
temperature coefficient.
The minimum recommended span [VRT – VRB] is 1.0 V. A
lower span will allow offsets and nonlinearities to become
significant. The maximum recommended span is 2.1 V due to
power limitations of the resistor ladder. The span may be
anywhere within the range of – 2.1 to + 2.1 V with respect to
ground, and VRB must be at least 1.3 V more positive than
VEE. The reference voltages must be stable and free of noise
and spikes, since the accuracy of a conversion is directly
related to the quality of the reference.
In most applications, the reference voltages will remain
fixed. In applications involving a varying reference for
modulation or signal scrambling, the modulating signal may
be applied to VRT, or VRB, or both. The output will vary
inversly with the reference signal, introducing a nonlinearity
into the transfer function. The addition of the modulating
signal and the dc level applied to the reference must be such
that the absolute voltage at VRT and VRB is maintained within
the values listed in the Recommended Operating Limits. The
RMS value of the span must be maintained
VRM (Pin 1) is the midpoint of the resistor ladder, excluding
the Overrange comparator. The voltage at VRM is:
2.1 V.
VRT
VRB
2.0
1 2 LSB
In most applications, bypassing this pin to ground (0.1
μ
F) is
sufficient to maintain accuracy. In applications involving very
high frequencies, and where linearity is critical, it may be
necessary to trim the voltage at the midpoint. A means for
accomplishing this is indicated in Figure 18.
Power Supplies
VCC(A) is the positive power supply for the comparators,
and VCC(D) is the positive power supply for the digital portion.
Both are to be +5.0 V,
±
10%, and the two are to be within
100 mV of each other. There is indirect internal coupling
between VCC(D) and VCC(A). If they are powered separately,
and one supply fails, there will be current flow through the
MC10319 to the failed supply.
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