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參數(shù)資料
| 型號： | MC12439FNR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 128K |
| 代理商： | MC12439FNR2 |
4
MC12439
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
390
PIN DESCRIPTIONS
Pin Name
Type
Function
Inputs
XTAL1, XTAL2
—
These pins form an oscillator when connected to an external series–resonant crystal.
S_LOAD
Int. Pulldown
This pin loads the configuration latches with the contents of the shift registers. The latches will be
transparent when this signal is HIGH, thus the data must be stable on the HIGH–to–LOW transition of
S_LOAD for proper operation.
S_DATA
Int. Pulldown
This pin acts as the data input to the serial configuration shift registers.
S_CLOCK
Int. Pulldown
This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising
edge.
P_LOAD
Int. Pullup
This pin loads the configuration latches with the contents of the parallel inputs .The latches will be
transparent when this signal is LOW, thus the parallel data must be stable on the LOW–to–HIGH transition
of P_LOAD for proper operation.
M[6:0]
Int. Pullup
These pins are used to configure the PLL loop divider. They are sampled on the LOW–to–HIGH transition
of P_LOAD. M[6] is the MSB, M[0] is the LSB.
N[1:0]
Int. Pullup
These pins are used to configure the output divider modulus. They are sampled on the LOW–to–HIGH
transition of P_LOAD. P_LOAD is state sensitive.
OE
Int. Pullup
Active HIGH Output Enable.
Outputs
FOUT, FOUT
—
These differential positive–referenced ECL signals (PECL) are the output of the synthesizer.
TEST
—
The function of this output is determined by the serial configuration bits T[2:0].
Power
VCC
—
This is the positive supply for the chip, and is connected to +3.3 V or 5.0 V (VCC = PLL_VCC).
PLL_VCC
—
This is the positive supply for the PLL and should be as noise–free as possible for low–jitter operation. This
supply is connected to +3.3 V or 5.0 V (VCC = PLL_VCC).
GND
—
These pins are the negative supply for the chip and are normally all connected to ground.
Other
PWR_DOWN
Int. Pulldown
LVCMOS input that forces the FOUT output to synchronously reduce its frequency by a factor of 16.
FREF_EXT
Int. Pulldown
LVCMOS input which can be used as the PLL reference frequency.
XTAL_SEL
Int. Pullup
LVCMOS input that selects between the XTAL and FREF_EXT PLL reference inputs. A HIGH selects the
XTAL input.
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